Synopsys and TSMC collaborate to certify Custom Compiler for 16FFC process

Synopsys, Inc. (Nasdaq:  SNPS) today announced a collaboration with TSMC to complete the certification for its 16-nanometer (nm) FinFET Compact (16FFC) process for a suite of Synopsys’ digital, custom and signoff tools from the Galaxy Design Platform. A key result of the certification is that Synopsys’ Custom Compiler solution is supported with TSMC’s 16FFC Process Design Kits (PDKs) through the iPDK standard. With multiple production designs for TSMC’s 16FFC process already underway, the tool certifications enable mutual customers to lower costs and increase reliability with TSMC’s FinFET technology.

The rapid adoption of FinFET technology and increasing functionality for automotive design applications is resulting in higher current densities and, therefore, more wires susceptible to electromigration (EM) effects, such as voids and short circuits. Additionally, the thermal profile of FinFET technology affects the temperature of surrounding metal interconnects, known as self-heating effect (SHE), which affects the possibility of EM failures over time. To address these challenges, TSMC enhances circuit simulation models that assess the impact of SHE on device reliability mechanisms, such as hot-carrier injection (HCI) and bias-temperature instability (BTI). Synopsys supports the new models with the latest versions of its popular HSPICE®, CustomSim™ and FineSim® circuit simulators. The enhanced reliability simulation solution enables designers to model circuit performance degradation over time – a key step toward improving long-term automotive design reliability.

To support TSMC’s 16FFC process, a suite of Synopsys’ digital, custom and signoff tools from the Galaxy platform are validated to handle enhanced design rules and reliability requirements for targeted applications, such as mobile, Internet of Things (IoT) and automotive. The certified tools deliver routing rules, physical verification runsets, signoff-accurate extraction technology files, statistical timing analysis that correlates with SPICE and interoperable process design kits (iPDKs) for the 16FFC process.

“The jointly developed enhancements for automotive design reliability and tool certification for TSMC’s 16FFC process are another significant milestone of the long-term collaboration between Synopsys and TSMC,” said Bijan Kiani, vice president of product marketing of the Design Group at Synopsys. “The latest enhancements and certification for custom, digital and signoff flows are enabling our mutual customers to deliver lower cost and higher reliability for their innovative designs in many application areas such as automotive, IoT and mobile.”

“Through our multi-year collaboration with Synopsys, we are now jointly delivering significant enhancements to improve design reliability for key applications including automotive ADAS and infotainment,” said Suk Lee, senior director of TSMC’s Design Infrastructure Marketing Division. “In addition, tool certification for TSMC’s 16FFC process signals to our mutual designer community that the Galaxy Design Platform tools are ready to be used with our 16FFC process for the development of their next-generation projects.”

Key Synopsys tools certified by TSMC for their 16FFC process include:

  • IC Compiler IITM place and route solution
  • IC Validator signoff physical verification
  • StarRC™ extraction tool
  • PrimeTime® timing signoff solution
  • Custom Compiler custom design solution
  • PrimeRail and CustomSim reliability analysis
  • NanoTime custom timing analysis
  • HSPICE, CustomSim and FineSim simulation

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