7) Real-World Performance of Scaled InGaAs Devices

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InGaAs is a promising channel material for advanced CMOS devices, but while laboratory prototypes have demonstrated its high performance, the true potential of the material at a realistically small physical size has yet to be shown convincingly. MIT researchers will show how novel intrinsic and extrinsic engineering with precise dimensional control led to unprecedented device performance in InGaAs QW(quantum-well)-MOSFETs that are bound by real-world CMOS scaling and footprint constraints. They fabricated thin-body self-aligned devices with 40-nm metal contacts having a contacted gate-to-gate pitch of just 150 nm and low resistivity. The devices demonstrated a record high transconductance of 3.1 mS/µm, and impressive electron mobility of more than 8000 cm2/Vs. As part of this work, the researchers developed a model to study the properties of nanoscale contacts for future devices.

PHOTOS, clockwise from the top: (a) InGaAs MOSFET cross-section schematic, and (b) transmission electron microscope image of a complete device with Lg=40 nm and 2.5 nm HfO2 gate dielectric. (a) Precise etching of the intrinsic region of the device is performed by dry RIE (a1) and digital etch (a2). The RIE stops a few nm above the channel surface. The number of cycles of DE is calibrated to compensate the uncertainty in RIE. The final channel thickness is controlled with 1 nm precision. (b) Correlation between number of DE cycles and final body thickness (tb=tbarrier+tchannel) and composition. (c) TEM images of finished devices with two channel thicknesses. In the extrinsic portion, the as-grown total channel thickness is 10 nm. In the intrinsic portion, the resultant tb are 4 nm and 8 nm respectively. TEM of tight-pitch MOSFET array sections with different pitch size (Lp), contact length (Lc) and gate length (Lg): (a) Lp=200 nm, Lc=40 nm, and Lg=130 nm; (b) Lp=150 nm, Lc=80 nm, and Lg=40 nm. (c) SEM top view of a complete device with 3-cell array.

(Paper #25.1, “Novel Intrinsic and Extrinsic Engineering for High-Performance High-Density Self-Aligned InGaAs MOSFETs: Precise Channel Thickness Control and Sub-40-nm Metal Contacts,” J. Lin et al, Massachusetts Institute of Technology)

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