MediaTek to deploy Synopsys IC Compiler for hierarchical design implementation

Synopsys, Inc. today announced that MediaTek Inc., a fabless semiconductor company for wireless communications and digital multimedia solutions, has initiated deployment of Synopsys’  IC Compiler place and route solution for hierarchical design implementation. Already in use for block implementation at MediaTek, this successful collaboration extends the deployment of IC Compiler to the full flow starting from hierarchical design planning, through top and block-level place and route to final chip assembly.

As the largest chip set supplier for the midrange smartphone and tablet market, MediaTek says it focuses on enabling customers to deliver premium products at an attractive price point. Characterized by longer battery life, fast processing times and fully-featured multimedia support, MediaTek chipsets include industry leading processor and graphics cores along with the latest in multiprocessing and wireless communications technology. To deliver these sophisticated chipsets and meet time to market windows, MediaTek wanted a predictable flow with fast turnaround times that could realize a design in the smallest area possible, with the lowest power and with blazingly fast performance. Having experienced firsthand the benefits of using IC Compiler at the block-level, MediaTek embarked upon a comprehensive collaboration to develop a hierarchical implementation methodology that would extend these benefits to SoC design.

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