The End of Scaling?

By Jeff Dorsch

Are we reaching the end of scaling?

Yes and no.

Let me explain.

The semiconductor industry has been able to “scale” the dimension features of chips steadily downward for decades. The good old, reliable planar bulk CMOS silicon process is on its way out, however, and scaling will have to go on without it. There seem to be no easy answers on how scaling will continue, with so many possibilities and variables to be considered.

Scaling might be an easier (not an easy) proposition if extreme-ultraviolet lithography systems were good to go for volume production of chips now, according to Brian Trafas, KLA-Tencor’s chief marketing officer. “EUV continued to be late to the marketplace,” he says. “It was going be for 14/16-nanometer, then 10-nanometer, now 7-nanometer.”

As EUV struggles forward, the industry is dealing with 193nm immersion lithography, which involves “more process steps, more cycle time,” Trafas says. “The focus on defectivity is really important. Everything needs to be defect-free.”

Dealing with all those defects is KLA-Tencor’s bread and butter, of course. “It’s good for us,” Trafas acknowledges.

Semiconductor Equipment and Materials International recognizes the general industry anxiety (or concern, at the minimum) about the future of scaling, and the topic is the subject of a Semiconductor Technology Symposium session on Wednesday, July 9. “Getting to 5nm Devices: Evolutionary Scaling to Disruptive Scaling and Beyond” will run from 9 a.m. to 12 noon in Moscone North. Attendees will hear from executives of GlobalFoundries, imec, Intel, Intermolecular, Sematech, and Soitec, along with professors at Stanford University and SUNY’s College of Nanoscale Engineering and Science. An Steegen, imec’s senior vice president of process technology, said at SEMI’s show-opening press conference on Monday that there are two different scaling roadmaps to consider – device scaling and system scaling. With the immersion lithography in use throughout the semiconductor industry, manufacturers are “battling complexity,” she said. Three-dimensional devices with FinFETs, 3D stacking in packaging, and emerging memory types could be answers to the scaling crisis, according to Steegen.

Once extreme-ultraviolet lithography becomes available, that will help the industry get through at least two process nodes, she added. FinFETs can “reset the roadmap,” Steegen said, and the industry has to “make sure the incentive is there” for 3DICs.

William Chen of ASE Group said of Moore’s Law and scaling, “The economic benefit is receding.” He looks toward system-in-package technology, with wafer-level packaging, 2.5D chip stacking, flip-chip packages, and wire bonding to help advance device scaling.

Robert Cappel, senior director of marketing at KLA-Tencor, said Monday, “Scaling is going to continue. It’s just going to be very, very hard.” Integrated device manufacturers need to collaborate with electronic design automation companies and fabless semiconductor companies to solve the scaling issues, he added.

The industry will need “virtual IBMs” – integrated efforts that can work on scaling from design to fabrication to packaging, Cappel asserted. That may come about when “the fabless powerhouses start to drive that,” he said.

Scaling still has several process nodes to get through. How that will be done will the subject of debate and interest for years to come.