Advanced Packaging Blogs
3D Blog by Phil Garrou
Dr. Phil Garrou
by Dr. Phil Garrou

Dr. Phil Garrou gives his insight into leading edge developments in 3-D integration and advanced packaging, reporting the latest technical goings on from conferences, conversations, and more.

IFTLE 38 ...of Memory Cubes and Ivy Bridges - more 3D and TSV

The 3D TSV announcements keep coming at a “fast and furious” pace and are becoming hard for all of us to keep up with. One announcement (this past week) and one rumor, are very important for the forward momentum of 3D IC integration. A few weeks ago Mark...

IFTLE 37 Advanced Packaging at Singapores EPTC

Like the IEEE ESTC meeting held in Europe [see IFTLE 26 Adv.Pkging at the 2010 ESTC] , Asia’s IEEE EPTC meeting, held every year in Singapore, is a sister meeting of the IEEE ECTC. ElectromigrationThe recent interest in electromigration is due to a number...

IFTLE 36 3D IC at the RTI ASIP part 2

Continuing our look at activities at the RTI 3-D Architectures for Semiconductor Integration and Packaging Conference ( 3D ASIP) held in Dec 2010 in Burlingame CA.Hiroaki Ikeda (Elpida), Tae-Je Cho (Samsung) and Mitsumasa Koyanagi (Tohoku Univ) discuss...

IFTLE 35 3D Highlights at the RTI 3D ASIP Part 1

This week we begin a look at activities at the RTI 3-D Architectures for Semiconductor Integration and Packaging Conference ( 3d ASIP) held in Dec 2010 in Burlingame CA . This is the longest running 3D conference (since 2003) and is focused on both...

IFTLE 34 3D IC at the 2010 IEDM

With the general belief that CMOS is becoming economically if not technically less and less viable as the industry continues to scale, it is to be expected that we will be seeing more and more 3D IC presentations at the IEEEs premier IC conferences namely...

IFTLE 33 Micron 3D Response, Sematech Standards, Leti 300 mm Line

Since the fall is always an busy time for professional meetings around the world, and nearly all microelectronic meetings are trying to give you 3D IC coverage, I’m having a tough time covering all of this information in a timely, chronological way. The...

IFTLE 32 3DIC in Munich part 2

Continuing our look at presentations from the IEEE 3DIC Conference held in November 2010 in Munich.IBM - 3D From a Server PerspectiveJeff Burns, IBM Dir of VLSI systems at Yorktown Heights, offered the perspective that 3D technology will require many...

IFTLE 31 Oxide Bonding Patent Litigation Has Begun

As has been expressed on IFTLE many times, full 3D IC requires: TSV, thinning and bonding. As of yet there is no real clarity as to who “owns” any of these technology although there have been many boisterous claims out there being made. In 2006 while the...

IFTLE 30 2010 IEEE 3DIC in Munich

In its new incarnation [see PFTLE 100, “3D IC in the City by the Bay” for historical perspective ] the IEEE 3DIC Conference met in Munich under the leadership of European co-chairs Peter Ramm (Fraunhofer EMFT Munich) and Eric Beyne (IMEC). Next years...

IFTLE 29 IEEE 3D IC Test Workshop Part 2

Continuing with our discussions on presentations made at the 1st IEEE 3D IC Workshop in Austin.NC State - TSV Test prior to stackDuring wafer test, it is valuable to be able to determine which TSVs are likely to yield when used, and which are not. To...

IFTLE 28 Testing 3D ICs Deep in the Heart of Texas

We have been discussing test as a significant issue for the commercialization of 3D IC technology for a few years now [see for example PFTLE 108 ”3DIC Test”, PFTLE 102 “The Four Horseman of 3-D IC Integration”, PFTLE 100, “3D IC in the City by the...

IFTLE 27 Era of 3D IC Has Arrived with Samsung Commercial Announcement

Back in Nov 2008 PFTLE called on Mick Jagger and “Mr Jimmy” to explain why we “don’t always get what we want". What we wanted two years ago were commercial announcements, from someone, from anyone using 3D IC technology. [ see PFTLE 53, “You Can’t always...

IFTLE 26 Adv Pkging at the 2010 ESTC

The ESTC (Electronic System integration Technology Conference) was set up to be the European equivalent to the sister ECTC (USA) and EPTC (Asia) conferences. This years conference in Berlin attracted ~ 480 attendees who saw 160 presentations, 4 poster...

IFTLE 25 IMAPS Part 2 Advanced Packaging

IBM Going Fab Lite ??Peter Clarke of EE Times is reporting that “ … IBM appears set to gradually back away from semiconductor manufacturing and to rely for its leading-edge silicon on Samsung and GlobalFoundries as foundry suppliers (link). If you are a...

IFTLE 24 IMAPS National Summary Part 1 - 3D Highlights

The IMAPS USA annual or “National”, as it is known, was held in Raleigh a few weeks ago. Rajen Chanchani of Sandia National Labs took over the helm as IMAPS President during this meeting with long time industry stalwart Voya Markovich next in line....

IFTLE 23 Xilinx 28 nm Multidie FPGA, Copper Pillar Advances at Amkor and Intel Looking at Foundry Options

Took a little time off to have Halloween with grandaughters Hannah and Madeline in Houston. If you’re a kid in America what a great holiday Halloween is. Basically, strangers give you candy for dressing up and pretending to be someone or something your...

IFTLE 22 Sources for Fanout WLP Continue to expand

FO-WLP (Fan-Out Wafer Level Package) is the general term for a type of package that employs wafer-level redistribution technology and supports formation of redistribution layers outside the chip area. FO-WLP has been discussed numerous times [ see Solid...

IFTLE 21 Sabishii VLSI Japan

In late Aug 2010 the VLSI Packaging Workshop of Japan, held every other year since 1992, became The International Symposium on Components, Packaging, and Manufacturing Technology (IEEE CPMT Symp Japan) with a Conference at the University of Tokyo....

IFTLE 20 ASE Examines Materials and Process Changes for Advanced WLP

Wafer Level Packaging (WLP) is one of the fastest growing segments of the chip packaging area. WLP began over a decade ago with very small packages having very few I/O. There is currently significant demand for much larger die (greater than 7 mm) with...

IFTLE 19 Semicon Taiwan 3D Forum Part 2

Continuing our look at the Semicon Taiwan 3D Technology Forum held a few weeks ago in Taipei.SiliconwareIn the past, SPIL has been rather silent about their plans for 3D IC. During his presentation at the 3D Forum, Carl Chen, VP of R and D, remarked that...

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