IFTLE 154 ICEP part 2: Thinning Effects on DRAM memory retention and More

By Garrou
Continuing our look at the Osaka ICEP conference held in April 2013.

ASET and Tohoku Univ

ASET and Tohoku Univ reported on the effects of thinning on DRAM and CMOS device characteristics. Basically the thinner the chip becomes, the more likely it is that mechanical stress will alter the device characteristics and that ionic impurities will contaminate the transistors.

Perhaps most importantly they thinned a 65nm NMOS DRAM to 200 um by mechanical grinding and then further thinned down to 30um by stress free CMP. They then examined the data retention time of the chip vs thickness (see below) . Data retention of the 30um thick device was ½ of that of the 200um device !


Dai Nippon Printing and AIST have examined the fabrication of interposers on 300 mm wafers and attempted to reduce cost.

500um thick interposers with 50um diameter TSV were fabricated on 300 mm wafers, insulted with SiO2 (TEOS based PECVD), filled with ECD Cu and the Cu CMP’ed to remove overburden (50-100um). They note that it was “difficult to form void free TSV due to he high aspect ratio (10:1).  Backside RDL was done with PBO dielectric (8um deposited and 50% shrinkage). They conclude that this process flow eliminates the need for wafer support since the 500um thinned wafers can be directly processed without support.

ITRI described their studies on the assembly of 3D stacked chip with 30um pitch microbump interconnects using both non conductive paste (NCP) and anisotropic conductive film (ACF).
The bump structure for NCP bonding is shown below. Cu/Ni/Sn solder micro bumps are connected to Cu/Ni/AU micro bumps. For ACF Cu/Ni/AU micro bumps are joined to Cu/Ni/Au micro bumps.


The NCP was an epoxy thermoset. Properties of NCP and ACF are shown below.  
The NCP assembled chip stack passed 1000 cycles of TCT and 1000 hrs of HTS without any failures. The ACF assembled stacks all failed after 85/85 testing for 100 hrs and showed 7% failure after 500 cycles of TCT.
ITRI also reported on the reliability performance of two capillary underfills with different Tg and CTE used for µbump bonding on a silicon interposer.

The 20 um pitch µbumps were composed of 5um Cu / 3um Ni / 5um Sn2.5Ag (solder cap). Thermo-compression bonding was used to interconnect the µbumps at 280 C for 15 sec and the gaps then filled by one of the two underfills. Their properties are shown in the table below.
Temp cycling data resulted in the Weibull plot shown below. The mean time to failure of underfill A (higher Tg) vs B was 20% higher.

Ishihara Sangyo Kaisha (ISK)
ISK described the development of oxidation resistant Cu nanoparticles (50nm). Cu ink was prepared and printed (13um thick). Thermal treatment [ 200 C for 60 min under N2 + O2 followed by 250 C for 60 min under N2 + H2] This thermal sequence “burns” off the organics and sinters the particles to form a 0.2um copper film with 0.5uΩ cm resistivity.
Osaka Univ
Osaka Univ reported that Cu to Cu joining can be accomplished using Cu nanoparticle paste (10-20nm particles in glycol protective solvent) They examined the shear strength of the joint vs thermal treatment atmosphere and temperature. The strongest bond (40 MPa) was achieved through 673 K bonding for 300 sec under 15MPa pressure with a N2/O2 atmosphere.
Tohoku Univ and Korea Institute of Industrial Tech
Tohoku Univ and Korea Institute of Industrial Tech studied the interfacial reaction between solder filled TSV and copper pillar bumps. Ti layer  (50 – 400nm thick) was used as barrier layer between solder and Cu pillar bump. Thermal aging for 500 hrs at 150 C was conducted and the interface examined. IMC thickness increased with aging time and as thickness of Ti increased the IMC thickness decreased.
For all the latest on 3DIC and advanced packaging stay linked to IFTLE…..





Dr. Phil Garrou gives his insight into leading edge developments in 3-D integration and advanced packaging, reporting the latest technical goings on from conferences, conversations, and more.

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