SEMICON West Lesson #2: Capital intensity & EUV - Solid State Technology
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SEMICON West Lesson #2: Capital intensity & EUV

by James Montgomery, news editor

July 26, 2010 - One thing appears undebatable about the future: semiconductor manufacturing is getting harder. DRAM players are running into "significant yield challenges" already, and will find more problems at 4X-3X nodes, notes Barclays' CJ Muse. While EUV lithography begins to get ready (or not) for prime-time, other challenging technologies are being worked into manufacturing -- increasing process control intensity, double-patterning (both NAND and DRAM and logic), high-k/metal gates, and other technologies. The upshot: capital intensity will almost certainly go up through 2011-2012, and maybe for several years out (Citigroup's Tim Arcuri suggested five years, during the Bulls/Bears panel session on Thursday.) Another Bulls/Bears panelist, Credit Suisse's Satya Kumar, added that we're now transitioning from technology spending to fab capacity spending -- which is 3× more intensive than shrinking device dimensions, he pointed out. "Capacity buys are only now beginning to emerge," agreed Muse in a post-show research note.

EUV litho gets lots of attention (see below), but there's another litho technology that's gaining momentum. Barclays' Muse says business for KrF tools -- which he calls "the best indicator in our minds of new capacity demand" -- is taking off, with pickup in demand led by TSMC (30+ units in 2010), Samsung (15 units), and Intel (10). And suppliers ASML and Nikon may be struggling to keep up, he says. "We had been modeling 60 units for all of 2010," Muse writes. But AMAT says it's now tracking 14 new greenfield fabs in coming years (DRAM >200K/WSPM; NAND >320K/WSPM; logic/foundry >350K/WSPM), so that unit expectation will have to be "materially higher."

More "lessons learned" from SEMICON West 2010:
Lesson #1: Good times here, for now
Lesson #3: 3D and packaging are hot
Lesson #4: Supply chain challenges
Lesson #5: Interests outside CMOS

The challenges in leading-edge semiconductor manufacturing and development are too daunting (technically and otherwise) for any one company to handle. That's the reasoning behind the IBM Common Platform Alliance, noted Gregg Bartlett, GlobalFoundries' SVP of process technology and R&D, in his Wednesday keynote address. (More on that here.) Even Intel's Andy Bryant played the "collaboration" card in his Weds. afternoon keynote, pointing to work between the IDM giant, universities, and supply-chain partners.

Collaboration isn't just for devicemakers, either. In the Tuesday afternoon "Executive Panel," GlobalFoundries' Tom Sonderman suggested equipment suppliers should take a closer look at the IBM alliance as a model for collaboration, in areas like automation, plug-in integration, and standards-based methodologies.

Whither EUV lithography?

"Just about anyone with a SEMICON badge had a view on what needs to happen with EUV," noted Credit Suisse's Kumar, with most concerns around mask inspection (particularly pattern at-wavelength inspection) and source power. "ASML has now probably issued a PO to Gigaphoton," he noted. Barclays' Muse suggested ASML will see orders "for as many as ten 3300 tools in 2H10."

One key EUV announcement came not from a supplier, but from a customer. In his Wednesday (July 14) keynote, GlobalFoundries' Bartlett revealed that the company will skip an EUV preproduction tool entirely -- confident in its collaborative efforts on an alpha tool installed at the U. of Albany nearby -- and will bring in a full production tool "as soon as it is ready" to its under-construction Fab 8 in Malta, NY, sometime around 2H12, and ramping to high-volume manufacturing in ~2015. Immersion litho and tricks like double-patterning will take the company to and through 2Xnm node schemes, he said, so EUV would be for the next node (~16nm). More than 60 EUV masks already have been shipped by GF's Dresden mask house, he noted. (Back in 2008 GF patterned a 45nm test chip using EUV.)

EUV also came up during the Q&A of the Bulls & Bears panel, when Ken Rygler asked the Wall Street analysts whether EUV would be ready sometime in the 1xnm window, or if ever. Barclays' CJ Muse responded that delaying EUV has been a good thing as issues such as inspection and source power get hammered out, and it helps areas like etch and process control as well. "We're bullish" on EUV eventually happening, probably sooner rather than later, he said. (Notably, Rygler was shaking his head at that response. "No one in the reticle inspection world believes it can get done, which is a fair point," Muse later told SST. "But I do think EUV tools will be ready by then. With the number of critical layers for DRAM going up so much, they will get it done.")


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