STATS ChipPAC launches flip chip packaging for advanced silicon nodes - Advanced Packaging
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STATS ChipPAC launches flip chip packaging for advanced silicon nodes


February 16, 2011 -- STATS ChipPAC Ltd. (SGX-ST: STATSChP), semiconductor test and advanced packaging service provider, launched fcCuBE technology, an advanced flip chip packaging technology that features copper (Cu) column bumps, bond-on-lead (BOL) interconnection and enhanced assembly processes.

As semiconductor devices are scaled to advanced wafer technology nodes of 45/40nm and below, innovations in package structure, design and assembly process are key to achieving high performance, cost-effective product solutions. fcCuBE technology delivers high input/output (I/O) density, high performance and superior reliability in advanced silicon nodes, according to the company. It enables flip chip packaging with a 20-40% lower cost than standard flip chips. Benefits of the new flip chip technology include high I/O escape routing density, scalability to very fine bump pitches of 80 micron and below with finer effective pitches, significant reduction of stress on ultra low-k (ELK/ULK) structures that has been proven down to 45/40 nanometer (nm) and 28nm silicon structures, broad fab node compatibility, higher resistance to electromigration, lead-free materials, and lower cost.

fcCuBE technology is based on STATS ChipPAC's proprietary BOL interconnect structure, which has been combined with Cu column bump to deliver an ultra-high I/O escape routing density with a finer bump pitch compared to standard solder bumps. The advancement enables more relaxed substrate design rules than standard flip chip packaging and provides scalability to very fine bump pitches.

Although copper is a harder bump material that can cause damage to ELK/ULK layers in finer silicon nodes, STATS ChipPAC has completed extensive thermo-mechanical simulation testing on fcCuBE technology with results demonstrating a significant reduction of stress on ELK/ULK structures, consistent with empirical data generated with 45/40nm as well as 28nm node product test vehicles.

"We are seamlessly deploying the core fcCuBE technology beyond traditional single-die flip chip packaging into more complex stacked/3D packages including Package-on-Package (PoP), Package-in-Package (PiP), flip chip/wire bond hybrid packages and next-generation Through Silicon Via (TSV) configurations," noted Dr. Han Byung Joon, EVP and CTO, STATS ChipPAC.

The fcCuBE will suit end products in the mobile/handheld, computing and high-end network/telecom markets, added Dr. Raj Pendse, STATS ChipPAC VP of product and technology marketing.

STATS ChipPAC Ltd. provides semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. Further information is available at www.statschippac.com

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