Reliability of PoP devices manufactured using underfill methods - Solid State Technology
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Reliability of PoP devices manufactured using underfill methods

Vicky Wang, Henkel Loctite (China) Co. Ltd., Yantai, Shandong, China, Dan Maslyk, Henkel Corp., Irvine, CA USA

Though many studies have investigated the board-level reliability of package-on-package (PoP) devices in relation to drop test and thermal cycling performance, packages manufactured with and without underfill and the impact of different underfill dispensing patterns (i.e., full underfill, cornerbond and edgebond), few studies have evaluated the effects of the underfilling strategy — such as underfilling the bottom component only or underfilling both top and bottom components — or the effects of solder alloy choice on the reliability of PoPs. This article presents findings from a recent study on the drop test reliability of PoP devices as a function of underfill dispensing type and PoP ball alloy type.

Today’s consumers continue to push the electronics industry to deliver mobile multimedia products with smaller and thinner designs, more functionality, better performance, and lower costs [1]. Because of the relentless drive to put more and more functions into highly miniaturized products, PoP has emerged as the leading 3D packaging configuration to address these challenges. Currently, PoPs are used predominately to integrate a high-density digital logic device in the bottom (base) package with high capacity or combination memory devices (i.e., DRAM and flash) in the top (stacked) package [1].

Although PoP technology is undergoing fast growth in portable electronic products such as mobile phones, digital cameras, PDAs, portable players, gaming, and other mobile applications [2, 3], its reliability issues are concerning many researchers and electronics manufacturers. With the lower profile cavity type PSetCSP stacking, board-level reliability was reported by Yoshida and Ishibashi [4, 5]. Yoshida et al. presented a detailed study on stacking yield versus the warpage impact for a 14 14mm PoP configuration [6].

In another study, Dreiza et al. compared different lead-free ball alloys and BGA substrate pad finishes to determine which solder joint and BGA pad finish structures offered the best board-level reliability, cost, and performance balance for the BGA interfaces [2]. Lee et al. reported the effect of underfill materials and dispensing patterns to the POP reliability performance under thermal cycling and drop test [7]. Toleno and Maslyk analyzed three different attachment methods for the PoP assembly process [3].

Test vehicles

For this analysis, Amkor 0.5-pitch 12 12mm PSvfBGA305 components were used for the bottom package and Amkor 0.65-pitch 12 12mm FBGA128 components were used for the top package. The test printed circuit board (PCB) was designed according JEDEC standards [8] and the board build-up structure was a 1-6-1 substrate material with a Cu-OSP surface finish. Components were then mounted on 15 non-via-in-pad component locations.

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Lead-free alloys evaluated in this experiment include SAC125 (98.3Sn1.2Ag0.5Cu) for the bottom component, SAC105 (98.5Sn1.0Ag0.5Cu) for the top component, and SAC305 (96.5Sn3.0Ag0.5Cu) for both the top and bottom components. Three underfilling types — no underfill, bottom only underfill, and both top and bottom underfill — were analyzed. The detailed experimental design is shown in Table 1.

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After the PoPs were assembled, underfill was applied using an automated dispensing system. The underfill used was a reworkable CSP and BGA underfill with low viscosity, fast flow rate at room temperature, and fast curing at low temperature to minimize thermal stress to other components. Detailed underfill properties are shown in Table 2. For boards numbered 1?6, only the bottom components were underfilled. For boards 7?12, both the top and bottom components were underfilled. Underfill dispensing was conducted using the parameters listed in Table 3. Following dispensing, the underfills were cured using a standard solder reflow process.

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Drop testing was conducted according to the JEDEC JESD22-B111 specification using a Landsmont model 15-D shock tester. Test boards were placed on the fixture with the component side down and then dropped. Electrical resistance was measured after each drop and, in this test, a change of resistance to infinite was defined to be a failure. Results are described below.

Figure 1. Underfill dispensing types: no underfill (top), bottom only (middle), and top and bottom (bottom).
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PoP drop test results

The drop test was performed with test conditions including shock pulse 1500G peak acceleration with a 0.5ms pulse duration (Fig. 2). Electrical resistance measurements showed that no failure occurred in the stacked package with both top and bottom underfilling. All failures occurred in the top package of the PoP devices that had bottom-only underfill. For the SAC105 alloy, drop test results after 40 drops for the package without underfill were similar to the package with bottom-only underfill, indicating that underfilling the bottom component only does not improve PoP reliability (Fig. 3).

Figure 2. Drop response during the drop test (1500G peak acceleration of 0.5ms pulse duration).
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Figure 3. PoP drop test results.
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After 150 drops, components that were underfilled on both the top and bottom showed no failure as compared to the failures noted with bottom-only underfill. This suggests that underfilling both the top and bottom devices of the PoP offers better drop test performance than underfilling the bottom device only. Ball alloy SAC105 had lower failure rates during the drop test than the SAC305 alloy. This result is consistent with other PoP drop testing [2].


This work suggests that while many documented PoP reliability studies have investigated the effect of factors such as ball alloy, pad finish and underfill pattern, the underfill strategy used is equally as important for reliability performance. Results from this study clearly indicate that underfilling both the top and bottom components offers better drop test reliability, as no failures were observed when this underfill strategy was employed. All drop test failures appeared in the PoP top package when a bottom-only underfill was used, indicating that top and bottom package underfilling delivers better drop test performance than underfilling the bottom package only. However, in instances where only the bottom package was underfilled, it was observed that the SAC105 sphere alloy offered better drop test performance than the SAC305 alloy.

PoPs continue to grow in use, as consumers demand more functionality in tighter dimensions. Indeed, PoP reliability will remain a subject of great focus over the next several years, as the industry gains more insight into their long-term, in-field performance. Underfill type and strategy will be key to enabling highly reliable PoP devices.


The authors would like to thank application engineers Beejal Mistry, Jeremy Alonte, Julie Bradbury, and Brian Toleno in Henkel’s Irvine, CA advanced research lab for providing the PoP test vehicles, design input, and thermal cycle testing. This paper was originally presented at the ICEPT-HDP Conference in July 2008.


  1. M. Dreiza, A. Yoshida, J. Micksch, L. Smith, “Stacked Package-on-Package Design Guidelines,” International Wafer Level Packaging Congress, San Jose, CA Nov. 2005.
  2. M. Dreiza, L. Smith, L., et al., “ Package-on-Package Stacking and Board Level Reliability, Results of Joint Industry Study,”
  3. B. Toleno, D. Maslyk, “ Process and Assembly Methods for Increased Yield of Package-on-Package Devices,” SMTA Pan Pacific Symp., Kauai, Hawaii, January 22-24, 2008.
  4. A. Yoshida, K. Ishibashi, “An Extremely Thin, BGA Format Chip-Scale Package and Its Board Level Reliabilty,” pp. 1335?1340 IEEE, Electronic Components and Tech. Conf. (ECTC), 2002.
  5. A. Yoshida, K. Ishibashi, “Design and Stacking of An Extremely Thin Chip-Scale Package,” pp. 1095?1100 IEEE, Electronic Components and Tech. Conf. (ECTC), May 2003.
  6. A. Yoshida, et. al., ”A Study on Package Stacking Process for Package-on-Package (PoP),” Electronic Components and Tech. Conf. (ECTC), May 2006, San Diego, CA.
  7. J. Y. Lee, T. K. Hwang, et al., “ Study on the Board Level Reliability Test of Package-on-Package (POP) with 2nd Level Underfill,” 2007 IEEE, Electronic Components and Technology Conference (ECTC), 2007 Proc.
  8. JEDEC Standard No. 22-B111, JEDEC Solid State Tech. Assoc., July 2003.

Vicky Wang received her masters degree at the Institute of Metal Research, Chinese Academy of Sciences and is an application engineer at Henkel Loctite (China), Ltd., Yantai, Shandong China 264006; [email protected]

Dan Maslyk received his masters degree in electrical engineering from Auburn U. and is a senior application engineer at Henkel Corp., Irvine, CA USA.


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