Burn-in and Test Socket (BiTS) Workshop Preview - Advanced Packaging
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Burn-in and Test Socket (BiTS) Workshop Preview

(February 26, 2010) MESA, AZ — The Burn-in & Test Socket (BiTS) Workshop will take place March 7–10, 2010 at the Hilton Phoenix East/Mesa Hotel in Mesa, AZ. More than 30 papers and posters will be presented; participants include end users and suppliers of test sockets, boards, burn-in systems, handlers, and packages; and other related equipment, materials, and services. The TechTalk session on PCB design, fabrication and assembly is booked full, as is the tutorial on RF socket characterization by Gert Hohenwarter, Ph.D. of Gatewave Northern Inc. Here are some of the show highlights.

Keynote Speaker
Ken Butler, Fellow at Texas Instruments, presents “Realizing the Benefits of Adaptive Test,” where he discusses adaptive test and its potential to reduce manufacturing costs. The keynote will take place Monday, March 8, at 9 a.m. Like most of the rest of the world, the electronics industry is under extreme pressure to drive out cost wherever possible. Outsourcing has become a way of life. IDMs in the US are nearly extinct since development and manufacturing costs must be amortized over a much larger product base. The ATE industry is a shadow of its former self and everyone is looking for the least expensive platform possible. It’s harder and harder to stay in business, let alone stay competitive. We hear a lot lately about adaptive test and the potential to use it to reduce manufacturing costs, but what is it really? Will adaptive test techniques make burn-in obsolete? How do we use these ideas effectively within my manufacturing flow? How hard is it to integrate into our existing test and data infrastructure? In this talk we will look at the history and evolution of adaptive test.

Distinguished Speaker
Tom Di Stefano, Ph.D., president of Centipede Systems, delivers a talk aimed at promoting and inspiring alternate test & burn-in operational approaches on Monday, March 8, at 1:30 p.m. Advances in Test-in-Tray technology have potential to improve greatly the productivity of burn-in and test for semiconductor electronics. With the growing complexity of IC devices, back end test operations consume an ever increasing portion of manufacturing cost. This trend cannot continue. Test-in-tray (TnT) enables full “lights-out” automation through all back-end processes where individual parts are not handled, manually or robotically, until pack and ship. The major wafer fabs have implemented full lights out automation years ago using the FOUP as a standard wafer carrier. A standard tray carrier serves the same role for back end processes. Automation equipment can be standardized around TnT for efficiency and a minimum of custom fixturing. A recently announced FlexFrame carrier overcomes problems that have hindered testing in tray or strip format. Although strip testing greatly increases test throughput where applicable, the method is limited to certain specific devices that can be tested in strip format. Further, dimensional stability, part placement, and cost of complex strip handlers have stunted adoption. The FlexFrame carrier overcomes these problems by holding devices in a dimensionally stable tray that is CTE matched to its mating contactor socket. Now, the placement and number of devices in the tray may be matched to ATE test capacity. The FlexFrame carrier allows easy alignment and insertion/extraction from the mating contactor socket, greatly simplifying the process and reducing the cost of automation. Test-in-Tray methods are applicable to a full range of semiconductor devices from WLP and TSV chips to complex BGA packages and MEMS sensors. TnT has the full potential to revolutionize the test industry – and the change is needed now. Open standards are essential.

View the complete program at http://www.bitsworkshop.org/advprog/advprog.htm#sessions

R&D Circuits Participates
R&D’s Circuits Tom Bresnan will be a speaker as part of Tech Talk on Sunday, March 7, at the start of the show, as well as presenting details of a new embedded component process on Tuesday afternoon. "R&D Circuits is a high-tech board and ATE fabricator focused heavily on engineering services and support. The BiTS show is an important show, both for our company and for our customers, and is very close geographically to our design center, so it is a great opportunity for us. We look forward to another good show this year," said Tom Bresnan. The company will also exhibit at booth A09.

Johnstech's Presentations
Johnstech will present on two different topics at the BiTS Workshop. Harlan Faller, senior technologist, will be presenting on Tuesday, March 9th at 10:30 a.m. The title of his presentation is, "Design of Experiment for Force vs. Current Evaluation of a 3x3mm Ground Insert." Faller will be discussing how ground inserts are an essential part of of a Test Contactor, especially when testing QFN and DFN packaged devices. His presentation will include data on the force vs. the current of a ground insert derived from a design of experiment (DOE) conducted on a 3 x 3mm metal alloy insert.

In addition, Jeff Sherry, senior RF product engineer, will co-present with Shawn Long from U.S Monolithics on Tuesday, March 9 at 11:30 a.m. The title of their presentation is, "Using Modeling to Simulate High Frequency Test Results." It will focus on how the modeling of a Contactor, load board and device can help predict test results. They will also discuss how the interfaces between the Contactor and load board and between the Contact and device can affect performance.  

Johnstech personnel will be on site during the expo at booth A10 to answer any questions and to share information on new Johnstech products.

Multitest’s Involvement
Multitest’s Valts Treibergs and Chris Cuda will present “Spring Probe PCB Pad Wear Analysis” during Session 2, which will take place Monday, March 8, 2010 at 3:30 p.m. During the product lifecycle of a semiconductor device, an ATE performance board may be used for millions and millions of individual DUT insertions. The life expectancy of the performance board is at least an order of magnitude greater than the individual set of socket interconnects (Pogo pins/spring probes in this case). Most investigations on interconnect reliability center on the probe-DUT interface. This study focuses on the probe to PCB interface. Since reliability testing over millions of insertions can be a very time intensive endeavor, a standardized method needed to be developed to observe wear in an accelerated manner. The test method needed to mimic an actual ATE environment as much as possible. A test system has been developed to wear PCB pads to 2 million cycles in under two weeks time. The test system setup and test methodology will be described in this presentation. A variety of spring probe geometries has been tested using the above methodology against standard ATE performance board pad configurations. Results will be shown for various spring probe geometries, including conical, spherical, crown, flat and flat-probe technologies. Socket cross-section is an important aspect for long-life PCB pads. A discussion and data will be presented that address socket preload and spring probe chatter on the longevity of PCB pads. The last critical element in optimizing PCB pad life is the surface finish of the pads itself.  Two popular surface finishes for pads have been studied and the results of wear testing will be discussed.

Tony DeRosa, product manager, Multitest, will present “New Probe Architecture Performance in High-volume Production” during Session 3, which will take place Tuesday, March 9, 2010 at 8 a.m. Semiconductor packages continue to challenge test engineers in terms of complexity, pitch, reliability and cost. The wafer-scale market has created a large demand for <0.5-mm high-volume testing technologies. Additionally, multiple functions are now being packed into one package and, in some cases, onto a single die. This creates the need for a variety of electrical capabilities such as low inductance, Kelvin contact, and high RF all in one contact set ? and at a lower cost for customers. After outlining some of the current and future challenges associated with packaging trends, DeRosa will present a nontraditional spring probe technology that targets high-volume production applications. This technology is a form of barrel-less architecture that is termed “flat” technology. Flat spring probes are made using nontraditional manufacturing processes rather than being turned on a lathe (as is the case with typical contact technology), stamped, etched or cut with a wire-EDM, as some alternative flat technologies are created. This presentation will compare and contrast the traditional spring probe architecture (barrel and plunger) with flat technology probes. Real high-volume production data will be presented comparing flat probe vs. traditional spring probe performance for critical parameters such as test yield, probe life and cleaning frequency. Multiple probe technologies from multiple suppliers will be compared in multiple applications.

Multitest’s Ryan Satrom and Valts Treibergs will present “An Improved Characterization Technique for Contactors” during Session 4, which will take place Tuesday March 9, 2010 at 10:30 a.m.One of the main challenges of interconnect characterization for contact manufacturers is the replication of actual test environment conditions. Several characterization techniques test and measure brand-new probes, but these techniques fail to account for performance degradation over time.  Alternative techniques test probes in a lifecycle test under lab conditions, but these methods typically do not include actual devices so the validity of the results are again questionable. The limitations of most lab characterization tests include the inability to test for several real-world variables such as solder migration, surface wear, oxidation, probe hardness, tip styles and force. Since none of these characterization methods can accurately predict performance once a contactor is placed in an actual test environment, it is necessary to evaluate other testing options. There are two main challenges to achieving accurate real-world test conditions ? the availability of a tester/handler system, and the availability of actual devices. By using in-house handlers and testers, and working with customers to obtain devices, Multitest is able to evaluate interconnects under conditions similar to high-volume environments. Multitest’s in-house tester uses a four-wire resistance measurement to ensure precise and accurate readings, and has been used to cycle actual devices up to 100K cycles. Using this setup, a range of variables has been tested including probe geometry, cleaning intervals, current levels, package type, cleaning effectiveness, and force. The results and conclusions from this testing will be presented.

The company will also showcase contactors in the BiTS exhibit. Its ECON contactor is a cost-efficient solution for high-power standard and plunge-to-board applications. The contactor features a cost of test advantage, maintenance friendly contact spring blocks and excellent electrical repeatability. The nanoKelvin contactor is a universal Kelvin contactor for high-power plunge-to-board applications. The nanoKelvin comes with full Kelvin capability combined with a plunge-to-board interface. The contactor features maintenance friendly contact spring blocks and excellent electrical repeatability. The Mercury contactor is a high-performance, cost-effective contactor for high-volume production test. The new architecture features a barrel-less probe design with dual fork redundant bias, excellent resistance stability and longer usable life, and superior reliability based on materials and design. Gemini Kelvin is a low inductance, high-frequency contactor for high-volume production. The Gemini Kelvin provides Kelvin contact for in-line and array applications and is field-proven with hundreds of contactors in high-volume production test environments.

Everett Charles Technologies (ECT) Contact Products Group (CPG) Exhibits Probes
The Bantam Series probes combine spring pin’s excellent RF and DC electrical characteristics, and a robust mechanical design for a long, useful life. ECT’s Mini-Mite Series probes typically are used on ball or flat area arrays and feature a unique single-ended design, providing very low, consistent DC resistance. The uniform design allows all three products to be used at the same test height. The single sliding contact cuts the failure mode in half and ensures very repeatable results. ECT’s CSP Series features multiple double-ended designs, providing wide flexibility in overall length, tip styles, spring forces, and exotic plating for lead-free applications. A work-hardened barrel design and tips manufactured with ECT’s Microsharp process ensure high quality and a long life. It suits testing flat arrays, QFNs or solder balls. ZIP Final Test probes provide spring contact pin technology for lab and production test applications. A scalable design allows for varying device-specific applications. The combination of “flat” plunger geometry and compression spring technology delivers high-yield test performance. It is available in high-performance and economy versions for WLCSP testing applications as well as WLBI. ZIP Burn-In vertically designed probes provide the next generation of spring contact pin technology for burn-in test. ZIP burn-in probes combine the “flat” plunger geometry and compression spring technology with economical design features for reduced cost. Burn-in probes allow socketing flexibility in hybrid test-based applications. High-Frequency Coaxial products from ECT provide instrumentation quality interfacing for broadband RF measurements up to 12 GHz.  K-50 Series probes can be used as Network Analyzer port-extending accessories for board-level impedance measurements that can be performed in the lab or in high-volume production environments with consistent and repeatable results.

See more exhibitors at http://www.bitsworkshop.org/exhibits/exhibitors2010.htm

For more information on BiTS, visit http://www.bitsworkshop.org/


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