BY GEORGE A. RILEY, Ph.D., contributing Editor
Flip chip on substrate assembly has been a placid technical field, with a mainstream high-volume manufacturing process carefully shepherded by production engineers towards raising yields and increasing line throughput. More recently, a growing storm of larger wafers, thinner packaging, higher levels of integration, questionable environmental diktats, and smaller consumer end-products is posing assembly requirements that the old ways may not meet. Here’s how some companies are responding to the challenges of 21st century flip chip assembly.
Amkor: Finer Bump Pitch
As silicon technology advances towards 65-nm processes, the combination of shrinking die and growing technical demands is forcing flip chip packagers to reduce bump pitches to 150 μm from their present “comfort range” of 200-225 μm, while accommodating the quirks of low-k dielectrics and high-temperature lead-free solders. Recent manufacturability and reliability studies by Amkor tested the limits of present assembly equipment and processes in meeting the new demands.1
Figure 1. Typical lead-free Sn/Ag bumps on 150-μm pitch. (Photo courtesy of Amkor)
Flip chip attach, fluxing, and underfill of finer-pitched die are primary assembly concerns. To explore possibilities, Amkor developed a 14.7-mm square test vehicle with low-k dielectric and 65-nm design features. Electroplated tin/silver (Sn/Ag) bumps on 150-μm pitch with 70- and 85-μm diameters, and nominal 75-μm heights, showed the effects of bump geometry on reliability (Figure 1).
While present die alignment and placing equipment gives satisfactory results at the smaller dimensions, Amkor found that fluxing requires closer-than-present control to make acceptable connections. However, a standard aqueous flux cleaning process removes the flux with no residues. Underfilling is slowed by the smaller die-to-substrate gap, with a dispensing time about twice that for 200-μm-pitch bumps. Standard underfill provides void-free coverage, but optimizing the underfill process will require reducing the filler particle size and tightening the size distribution.
Temperature cycling to condition B (-40° to +125°C) caused no electrical failures on the test vehicles at 1,500 cycles. Sample bump cross-sections after cycling displayed no signs of solder cracking. The company concludes that with some fine-tuning their present materials, equipment, and assembly processes can support 150-μm pitch.
Endicott Interconnect: Thinner Substrates
Besides the benefit of thinner packaging, thinner substrates offer increased circuit density, improved electrical performance, and easier manufacturability. Thin substrates allow closer via pitch with smaller capture pads, aiding circuit routing. The thinner dielectric keeps signal lines closely coupled to ground planes, allowing closer line spacing. The shorter package-to-die path reduces inductance. A thin substrate reduces via laser drilling distances, and the reduced via aspect ratio aids plating.
However, thinner substrates are more susceptible to warping than thick ones. Endicott Interconnect reported overcoming several flatness challenges of high-density, thin-core substrates.2 Figure 2 is a cross-section of a typical dense-core, eight-layer (2-4-2) substrate used in Endicott’s tests. The nominal thickness of the inner core dielectric is 100 μm, and all other dielectric layers are 50-μm nominal thickness. Both the signal traces and the ground/voltage islands may be placed on any of the eight copper planes, giving considerable design flexibility.
Taming thin substrates requires maintaining flatness through every step of assembly. This includes controlling the effects of carrier attributes on carrier flatness, underfill on post-cure flatness, and lid attachment on post-lidding flatness.
Carrier flatness depends on the design and the core material. Thin organic carriers warp more than thick carriers from the thermal expansion mismatch of core and copper. In one simulation, a predicted warpage of 300 μm for a 100-μm core carrier dropped to 150 μm when core thickness was increased to 600 μm. Substituting a low-expansion 100-μm core reduced the predicted warpage to 125 μm. Changing the design to a “balanced” layout with copper symmetry from plane to plane further reduced warpage to below 50 μm. Experimental verification showed that the low-expansion 100-μm core with a balanced layout reduced actual warpage from about 200 μm to 38 μm, matching the performance of thick FR-4 cores.
Figure 2. Cross-section of typical dense-core 8-layer substrate. (Photo courtesy of Endicott Interconnect)
Underfills with a range of mechanical properties were tested with thin-core carriers. While these produced differing amounts of module warpage after cure, even the most warped resulted in acceptable module flatness after bonding to a suitable cover plate. The tight mechanical coupling between the substrate and the cover plate produces modules with flatness equivalent to modules that have added metal stiffeners.
STATS ChipPac: Bumps on Leads
Bump-on-lead (BOL) is an alternative path to fine-pitch high-I/O flip chip assembly.3 BOL bonds the bumped die directly to prepared substrate leads, rather than to conventional substrate capture pads. Making the substrate landing pad the trace itself saves enough space to allow routing an additional trace between the bumps. The standard 105 μm escape pitch is reduced to 70 μm, without changing the trace width or spacing. This space saving potentially could allow about 70% of flip chip ICs to be assembled with single escape layers, and lead to a wider use of less costly thru-hole laminate substrates.
STATS ChipPac’s test die was 17-mm2, with a total of 4,751 high-lead (97Pb/3Sn) bumps. Three substrates - one ABF build-up and one laminate for BOL, and a conventional capture-pad reference substrate - all had tin/lead (Sn/Pb) eutectic solder on copper pads. Assembly characterizations included accelerated fatigue testing without underfill, and full package testing with four different underfills.
Solder joint cross-sections of the BOL assemblies showed a unique shape. Eutectic solder wicking from the narrow substrate leading up to the spherical high-lead bump left a smoothly tapering shape resembling a hot-air balloon (Figure 3). Finite element analysis shows that this provides additional strain relief by moving the highest strain concentrations away from the vulnerable bump-to-die interface. The magnitude of maximum plastic strain concentration in the BOL buildup structure was calculated as 35% below that of the conventional structure.
Figure 3. Profile drawing of bond from chip to substrate lead.
Accelerated fatigue testing without underfill supported these calculations, with the BOL buildup structure superior in time to first failure, and at least as reliable as the conventional structure overall.
Underfilled samples with this bump structure subsequently passed full JEDEC qualification testing.
TDK: Thermosonic onto FR-4
Gold-to-gold thermosonic flip chip assembly is a flux-free, low-stress approach, with heating generally below 150°C and load forces less than 100 g per bump. Thermosonic mounting accuracy of 8 μm and bump diameters under 50 μm support substrate pitches below 80 μm.
Until recently, thermosonic assembly had been limited to typically 20 or fewer simultaneous connections. However, TDK Corporation recently reported good reliability data for 100-bump chips thermosonicly assembled onto FR-4 substrates.4
The thermosonic process connection is made by solid-phase bonding between the two gold layers. Diffusion of gold (micro-welding) under load, and ultrasonic power, create the gold-to-gold connection as a second bond layer that is void-free and monolithic. Reliability testing of underfilled assemblies included 1,000 cycles of air-to-air thermal shock from -55° to +125°C and 168 hours of 85°/85% temperature/humidity environmental stress testing with no failures.
Flip chip assemblers are feeling the hot breath of wafer-level packaging on their necks. The International Electronics Manufacturing Initiative (iNEMI) sees stacked die and thin wafers as gaps in its 2007 roadmap. Some die- and wafer-stack approaches are already moving towards the front end of line (FEOL), with via drilling done before wafer first metal. Flip chip assemblers without wafer-based packaging capabilities may find themselves playing on a shrinking field.
- Nichols, L., Engel, K., et al, “Preliminary Manufacturability & Reliability Data for 150-μm Pitch Lead-free Plated Interconnect FC using 65-nm Low-k silicon,” IMAPS Device Packaging Conference, Scottsdale AZ ,USA, March 18-19, 2007.
- Jadhav, V., Moore, S., et al, “Flip Chip Assembly Challenges Using High Density, Thin Core Carriers,” ECTC 2005, Lake Buena Vista, FL, USA, May 31-June 3, 2005.
- Pendse, R., Kim, KM, et al, “Bond-on-Lead: A Novel Flip Chip Interconnection Technology for Fine Effective Pitch and High I/O Density,” ECTC 2006, San Diego, CA, USA, May 30-June 1, 2006.
- Couts, P. and Kawahara, M., “Flip Chip Ultrasonic Gold to Gold Interconnect for Small Die Using Organic Substrates,” IMAPS Device Packaging Conference, Scottsdale, AZ, USA, March 18-19, 2007.
GEORGE A. RILEY, Ph.D., contributing editor, may be contacted at Flip Chips Dot Com, 210 Park Ave. #300, Worcester, MA, 01609; 508/753-3572; E-mail:[email protected]