Broadening the platforms for system-in-package solutions - Solid State Technology
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Broadening the platforms for system-in-package solutions


Claudio Truzzi, Steve Lerner, Custom Silicon Configuration Services (CS2), Zaventem, Belgium

overview
System-in-package technology is allowing progress in miniaturization, performance, and cost reduction leading to tremendous advances in portable electronics. Significant challenges with system-on-chip technologies make SiP an attractive option for many applications. Integrated passive components are a key part of the SiP approach.

In the early 1990s, when computer desktops and workstations were the driving force for the semiconductor industry, single chip packaging was the dominant technology in the back-end of the IC industry. The mass market was focusing on the DRAM industry — DRAM cost could be 10-15% of the cost of a desktop computer. Memory hungry applications such as numerical analysis and graphic intensive applications (such as video games) were the driving force.

The wireless communication market is today the main driving force for the semiconductor industry. Figure 1 shows how the wireless application market overtook cars and personal computers in the mid-90s, both in volume and growth rate [1]. The requirements for the IC back-end industry changed accordingly, moving toward smaller and lighter packaging solutions.


Figure 1. Worldwide sales of cars, PCs, and mobile phones.
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Area array packaging has become an enabling technology to address the needs of customized package solutions to reduce size, weight, and pincount at the second level of interconnection. This packaging technology includes pin grid array (PGA), ball grid array (BGA), and chip scale packages (CSP), with BGA playing the largest role and CSP showing the largest relative growth. The compound annual growth rate (CAGR) of the area array packaging market is over 46% [2]. More specifically, the BGA/CSP family is projected to grow from 4% of the total unit production in 1999 to nearly 13.5% in 2003. The BGA/CSP family represented 27% of the $19B total packaging market in 1999 and is expected to represent 62% of the $29B packaging market in 2003. In 1999, this percentage was expected to be 43% in 2003, demonstrating that the growth is increasing faster than expected. Figure 2 shows the packaging revenue forecast and percentage distribution by package family [2].

One reason that area array packaging has become an enabling technology is its potential to offer custom and semi-custom solutions with very short cycle times. The interconnection and pin location flexibility give IC designers the option of being in control of the packaging development, rather than being forced into a given, standard package format. Package design and characterization has become an integral part of the chip development flow. The chip/package co-design approach is replacing the traditional sequential chip+package+assembly production flow.


Figure 2. Packaging revenue forecast and percentage distribution by package family.
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BGA packaging has enabled the proliferation of mobile phones, and the standard package applications are: high performance RF, digital base band, mixed signal integrated circuit, and power management.

Emerging applications that are driving package developments include: MP3 processor, camera/video and voice processing, GPS chipset, wireless application protocol (WAP), Bluetooth, universal mobile telecommunication system (UMTS), and wideband code division multiple access (W-CDMA) protocols.

The wireless market requirements are stimulating a number of new single chip packaging (SCP) solutions and opening up the way for a new packaging approach — the system-in-package (SiP).

New SCP solutions
New SCP solutions fostered by the wireless telecom market focus on slim design (ultra-thin BGA), packaging efficiency (stacked CSP), signal integrity (flip-chip in package, or FC-BGA), and environmental issues (Pb-free package). The main challenges are thermal management, mechanical stress build-up control, and first-level and second-level reliability. Detailed discussions on these packaging solutions can be found in the literature [3].

Emerging system-in-package solutions
System-in-package solutions consist of assembling a few ICs in a single package. Passive components, if required, can be assembled as discrete components or integrated within the interconnection substrate. The main advantages of SiP are: use of readily available off-the-shelf components, relative ease of mixing device technologies, very short cycle times, and no intellectual property issues.


Figure 3. Relative price dilution and mask cost increase for SoC..
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Area array packaging technologies such as BGAs offer a number of advantages as a system integration technology, including: multilayer routing, a 2D interface at the board level, mixed assembly processes, small size, a choice of substrate material, and increased reliability. It is becoming the technology of choice to integrate different components in one package.

Although the SiP approach is derived from the multichip module (MCM) concept, it is worth noting that today's SiPs have significant differences from the MCMs of the early 1990s. A decade ago, large module size, very large component counts, custom packages and test sockets, and very low yield confined MCM solutions to very high-end niche markets such as military, aerospace, and supercomputer applications.

The integration level reached by microelectronic technologies today makes it feasible to realize a complete high-level electronic function on a single piece of silicon (system-on-chip, or SoC). However, several issues, such as area efficiency, wafer yield, and mask cost, usually play against this approach. Long development time is another issue for SoC. New mobile phone products are released every six months, while the development of a new SoC can require up to one year. The following quotes and Fig. 3 provide some insight.


Figure 4. Multichip package with a) side-by-side chip placement, and b) stacked chips.
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"A couple of years ago, we really thought that the embedded DRAM model would be the panacea for many applications," said John Kelly, GM of IBM Microelectronics. "It's not always the right thing. In many applications, it still remains much cheaper to do it with multichip modules. It gives you satisfactory performance and often for lower cost." [4]

"We have systems-on-chip now that are really 'system on chips'," said John Dickson, president of Lucent Technologies' Microelectronics Group. "We do it that way because it's most cost-effective, and the customer will prefer it that way because it offers more flexibility." [4]


Figure 5. Microcontroller module for automotive applications (Source: FhG-IZM).
Click here to enlarge image

SoC can be regarded as an inherently inefficient solution, with high-value logic blocks being diluted by low-value memory or analog blocks, while the mask levels (i.e., the production cost) increase [4].

As an example, consider CMOS wafer production for microprocessors or DSPs. Figure 3 shows how the average selling price per square centimeter of wafer is diluted by using 20% of the real estate to integrate other technologies (FPGA, analog, or memory), assuming the normalized average selling price value for logic technologies (DSP or microprocessor) equals 100 (left axis) [4, 5]. The technology mix means a larger number of mask levels. The same figure also shows the related mask cost increase, assuming the normalized value for logic technologies = 100 (right axis).

SiP can be divided into three categories: multichip package (MCP); MCM; and integrated package (IP). This subdivision describes differences in the internal structure. From the external point of view, no major difference can be spotted, as they all look like single chip packages. There is no difference whatsoever in assembling SiPs or SCPs onto a board. This is a fundamental point for SiPs — by disregarding it in the early 1990s, MCM manufacturers limited the possibility of MCM adoption for mass volume production.

Therefore, today's trend is to limit the number of active components in an SiP to below 5 (usually 2 or 3), and the number of discrete components to about 10, in order to use standard package body sizes, simplify the assembly process, and increase the final yield. The only exception to this rule is given by the IP solutions, where passive components are embedded into the package body and their number is therefore not limited by assembly issues.

Three major factors have driven electronics manufacturers to reconsider system-level packaging technologies:

Higher integration at the IC level. The same functionality of a large early 1990s MCM is today available in one or two chips. This allows size reduction and the use of standardized package body sizes.

Routing flexibility of area array packages. The internal connections required by MCMs have historically forced the introduction of an intermediate level between components and boards. This did not fit within the traditional electronics industry supply chain. With today's BGA substrates, internal routing comes "for free" and is taken into account at the component level, making it totally transparent to the board assemblers.

Passive integration. Ceramic and thin-film on glass technologies allow the integration of passive components within the interconnection substrate. This facilitates drastic size reduction, better performance, higher reliability, and lower cost in surface-mount component driven applications such as RF front-ends for wireless communications.

Multichip packaging solutions
As the name implies, MCPs involve more than one chip/package. The packaging architecture could be either chips attached side-by-side (Fig. 4a) or stacked chips (Fig. 4b). MCPs typically do not include discrete components.


Figure 6. Embedded inductor in thin film on glass.
Click here to enlarge image

Most side-by-side MCPs include just two ICs with no connection between them. The resulting package footprint is very close to the sum of the area of two separate single chip packages. This package solution is adopted for logic and memory chips and is purely cost-driven. When internal connections between the ICs are required, they can be implemented either with direct chip-to-chip bonding or with the use of internal routing connections.

For stacked MCPs, the focus is on the reduction of board usage. The stacking involves a precise control of assembly processes, and the feasibility may vary due to highly customized requirements. Typical applications are for SRAM + FLASH memories, which can share the same address and data bus terminals.

Multichip modules
An MCM could be described as a subsystem package. MCMs allow for a wide assembly and IC technology mix: SMDs, wirebonded ICs, flip-chip, logic, memory, analog, and RF ICs. The value-added is typically higher than for MCPs, since MCMs tend to be more customized. Footprint reduction and modularization are major drivers for this approach.

Figure 5 shows a module for automotive applications built around a microcontroller chip. The module consists of five ICs and a large number of passive components. The module footprint is smaller than the standard single chip package of the microcontroller.

Integrated packaging
Probably one of the strongest points of the SiP approach is the ability to remove large numbers of discrete components by integrating them into the interconnection structure. The "embedded passives" can be integrated in different substrate types: laminate, ceramic, or thin-film on glass. This approach is ideally suited for most electronic circuits and provides the best value-added when applied to functions where the largest real estate is taken over by the discrete components. The high-frequency part of transceiver circuits for telecommunications (the so-called RF front-end) is today the best candidate for this technology. Other interesting applications include decoupling capacitors, biasing networks, and signal bus conditioning.


Figure 7. Cross-section of thin-film technology with embedded passives.
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For frequencies above 2GHz, tight geometric tolerances, good lot uniformity, and lot-to-lot reproducibility are key for high quality components (i.e., with low losses at high frequency). An important challenge in embedded passive components consists of ensuring the link between design and technology, or, in other words, in linking the performance to geometrical parameters. As an example, when designing a spiral inductor, a designer can vary four independent parameters in order to obtain a specified inductance value at a given frequency range: diameter (D), conductor width (W), conductor spacing (S), and number of turns (N). Any combination thereof has a different impact on the quality factor Q of the component, which is a key element for circuit performance. It is important to tightly characterize a given technology in order to select the correct mix of values delivering the highest Q factor. (See Fig. 6 for an example of an embedded inductor and measurements of its Q factor.)

Thin-film on glass is emerging as the technology of choice for these applications, thanks to the superior tolerance and reproducibility control over laminate or ceramic technologies. The new highly automated thin film manufacturing lines based on large area panels or 200mm wafers enable a cost parity with other technologies. An example of a thin-film on glass build-up structure for an RF front-end application is shown in Fig. 7.

Embedded passive component technologies can be used in two different ways:
1. To manufacture integrated passive devices (IPD) such as resistor and capacitor networks or filtering and biasing circuits. IPDs are also called "passive chips," and they can be mounted in BGA-like packages together with active devices in an MCP or MCM package.


Figure 8. RF front-end module (Source: IMEC).
Click here to enlarge image

2. To fabricate embedded passive modules that implement the concept of "functional interconnection." The substrate not only interconnects active devices (as traditional substrates do), but it conditions the electrical signal as well by means of integrated filtering and biasing functions.

The main steps of a typical assembly process flow of the latter solution would be: 1) bond the embedded passive substrate onto the BGA substrate, 2) bond the ICs and the discrete devices onto the embedded passive module, 3) wire bond all components, 4) encapsulate the module by mold transfer techniques, 5) apply solder balls to the bottom side, 6) singulate the packages, 7) laser mark and inspect, and 8) perform final functional test.

Figure 8 shows an RF functional block realized with thin-film on glass and utilizing the embedded passives approach. This module includes BJTs, diodes, and passive components, and it measures 7.5mm on each side. Resistance values up to 200W/sq, capacitance values up to 0.8nF/mm2, and inductance values up to 50nH with a quality factor Q greater than 50 can easily be manufactured in volume with this technology. Up to 100 passive components per square centimeter can be embedded using thin-film technology, allowing the integration of complete Bluetooth front-end modules in less than 1cm2. Thin-film on glass is opening up the path to a new packaging definition: system-in-CSP.

Conclusion
The wireless telecom market sector is driving radical changes in the electronics industry, stimulating a number of new packaging solutions. Size, performance, reliability, cost, and environmental issues are the major drivers of this shift from device-oriented to function-oriented packaging. Along with emerging solutions, old concepts such as flip-chip and MCMs are being revitalized, with a better understanding of how to integrate them into the new automated and flexible infrastructure of modern back-end packaging foundries.

The new packaging foundry concept calls for a broadening of the platforms historically available in these houses. Traditional wire bonding and encapsulation are still there, but new capabilities needed include system-level interconnect design and characterization, system simulation, final test, and even wafer processing tools for wafer-level packaging and thin-film substrate fabrication.

References

  1. Paul Collander, "Roadmaps for Design of Future Mobile Communication Terminals," Proc. of IPSS Workshop at Semicon Europa, pp. 54-60, 1999.
  2. Sandra Winkler, The Worldwide IC Packaging Market, 2000 Edition, Electronic Trend Publications, San Jose, CA, 2000.
  3. S. Lerner, C. Truzzi, "Site Synergy and Short Cycle Time Drive Advanced Packaging Assembly in Europe," Chip Scale Review, pp. 42-46, March-April 2000.
  4. Robert Ristelhueber, "Expanding Role of Packaging Seen Relegating SoC to Niche Status: System-chip May Topple," TechSearch News, 1086, Nov. 8, 1999.
  5. Sematech Int'l., ITRS, 1999 edition, http://www.itrs.net/ntrs/publntrs.nsf.

Claudio Truzzi received his degree in electrical engineering from the University of Bologna, and his PhD in metrology from the Polytechnic University of Torino. He is the director of engineering and technology development at CS2, Hermes Center, Hermes Straat 2A, 1930 Zaventem, Belgium; ph 32/272 00000, fax 32/272 00001, e-mail [email protected]

Steve Lerner received his bachelors' in mechanical engineering from the State University of New York, Stony Brook. He was the managing director of Amkor Anam Euroservices, and the VP of worldwide marketing and sales for Swire Technologies. Lerner is a member of IEEE CHMT, IMAPS, and MEPPE.

 

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