Wafer manufacturing issues for III-V optoelectronics - Solid State Technology
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Wafer manufacturing issues for III-V optoelectronics

Optoelectronic devices using III-V compound semiconductor materials are increasingly central to optical communications. One of the III-V materials systems on which they are based - indium phosphide (InP) - is of particular importance because it enables devices with the crucial cost and performance characteristics that system vendors require, now and in the future.

InP provides monolithic integration of multiple functions (e.g., lasers, modulators, and variable optical attenuators, or VOA) on a chip, and offers higher-performance, lower-cost solutions. InP is also a very compact, lower-cost technology for 2.5Gbit/sec and medium-reach systems operating at 10Gbit/sec for metro transmission.

While this trend is very good news for system vendors and their carrier customers, it presents considerable technical challenges for wafer fabrication. III-V semiconductors present different processing challenges and material complexities than silicon, and economically producing increasingly complex integrated devices in volume is becoming a major issue.

Much revolves around process control and its influence on yields. The fabrication process of a modern III-V device is long and complex.Feature size and the ability to control the dimensions (vertical and lateral) of the structures making up the devices are obviously critical, but increasing integration and device complexity mean that nonplanar wafers have to be processed as well as the simpler planar ones. Topography issues bring an additional complexity toprocess control, particularly in multistage epitaxy where there may be three or four growth stages; maintaining the quality of the later process stages can be difficult.

Ideally, the III-V semiconductor industry needs to move closer to the process methodologies of the silicon industry. One of the characteristics of that industry is the wide use of test vehicles - specific test features added to a wafer during processing that allow manufacturers to dispense with 100% functionality testing of the completed chips. For complex integrated devices, this represents a considerable savings in effort and cost.

Parametric testability and device modeling

One of the key challenges facing the manufacture of III-V optical components is providing complete parametric testability of a wafer and then relating the measured performance distributions back to critical areas of process control within the wafer fab. This ability has two main benefits: It provides known good die with high yield for the subsequent stage of module/component manufacture, and it drives process yield improvement at the wafer level.

To achieve parametric testability means developing test features that allow, among other things, the building blocks of device functionality to be measured independently and then related to the device’s overall performance, for which the influence of the wafer fab process is well understood. Sophisticated device modeling is necessary to understand how process parameter variation is related to changes in device functionality.

Bookham is modeling optical modulators fabricated on an InP platform. Parameters include loss, operating voltage, and extinction ratio, as well as all the various electrical parameters, such as leakage current. The modulators consist of a Mach-Zehnder interferometer section of two closely spaced waveguides; splitter and mixer functions provided by multimode interference (MMI) structures; and integrated VOAs, detectors, and input/output spot-size converters (Fig. 1). The devices are tested at the bar level, ~20 chips, which contains test vehicles that assess the performance of the waveguides, MMIs, filters, and so on, independently.

Figure 1. InP modulator chip showing the integration of the modulation, VOA, and detector sections with input and output spot-size converters for enhanced coupling efficiency. (Source: Bookham, 2004)
Click here to enlarge image

The performance of these test structures can be directly related to geometric control during the lithography, deposition, and etching processes. For this purpose, a fully automated optical alignment and test facility has been developed that also allows the data to be processed into wafer maps of device performance for translating the root cause of spatial parametric variation into spatial process variation across a wafer.

The use of test features does not amount to any significant loss of wafer area (~1% or so in total), as only a few are needed around the wafer. The technique gives very focused results. For example, the loss contribution of waveguides, metallization, connections, filters, and MMIs to the total chip loss can be measured from the test features. Clearly, if all chips on a wafer are measured at twice their expected loss, the wafer is faulty, and if all the excess loss is accounted for by the waveguide contribution, that immediately points to a particular process step.

The overall practical impact is not limited to improving process yield. Redesign loops are considerably shortened. If the chip does not meet the final product requirements, the extra information available about all the subcomponents’ behavior makes it much easier to see how they interact, and this makes design iteration less arduous. Therefore, it is possible to design in order to achieve a predicted yield distribution, rather than just a few points in a model - a highly important point.

Inherent limitations to using test features in optical devices still need to be overcome. The optical nature of such devices means that it is not possible to measure the optical test features during the various process stages (which would be ideal for optimum control on a stage-by-stage basis). They can be measured only at the end of the production process when the wafer is cleaved and coated. In practice, they are measured at the same time as the finished chip is measured. This still allows for monitoring of the process control around each of the separate features, however, as opposed to obtaining a single measurement of the overall performance of the device.

Figure 2. Wafer map showing a radial dependence with a variation of ~2dB from the center to edge of the wafer. (Source: Bookham, 2004)
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A key to improving yield is to have detailed maps of the performance parameters’ spatial variation across the wafer because this indicates a process parameter spatial variation. Figure 2 shows an example where the coloring has been enhanced to illustrate the variation within a parametric spread, showing an area yield of ~80%. This allows an obvious and useful variation pattern to be observed. For smaller numbers of larger chips, interpretation is much more difficult.

Looking ahead

For the future, an intriguing notion - and another big technical challenge - is to alter the design of the III-V devices themselves and incorporate internal features that can be used as test vehicles. The tradeoff would be simpler testing of a more complex chip, and since chips are becoming more complex anyway, this tradeoff could be very attractive.

Ultimately, test features for optoelectronic devices need to be developed so that they become the only necessary measurements to pass a wafer with high yield, which has been the situation in the silicon industry for some time.

Andrew Moseley is product engineering manager at Bookham’s Caswell Wafer Fab, Towcester, Northamptonshire, NN12 8EQ, UK; ph 01-327-356-336, e-mail [email protected]

Joy Thompson is process engineering manager at Bookham’s Caswell Wafer Fab.


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