(August 10, 2010) -- In a recent report, Yole Développement asks if next-generation package substrates are myth, niche, or high-volume necessity? Several companies are investigating silicon interposers and there is great interest in the topic, but there is no clear consensus on applications and timing for adoption.The current incarnation of the silicon substrate is a simplified version of the full 3D-TSV being developed by many companies, and TechSearch International released its forecasts for silicon interposers, based on interviews with IDM, OSAT, and substrate companies. Both analyst forecasts are summarized below.
Substrates can be produced with TSVs and are an appealing interim step to some companies because they offer fewer challenges than vias through active silicon, according to recent research by TechSearch International.
For this study, TechSearch International interviewed integrated device manufacturers (IDMs), outsource semiconductor assembly and test (OSAT), and substrate companies. This report details the potential applications for silicon interposers as well as current and future suppliers. Interposer dimensions are provided, including interposer thickness, via diameter, and via pitch. A market forecast for silicon interposers is provided. This analysis is a part of TechSearch’s Advanced Packaging Update Service. For additional information see the data sheet (Advanced Packaging Update: Vol. 1-010) at: http://www.techsearchinc.com/index.html
Listing all of the 3D silicon/glass interposer opportunities by application, Yole’s report provides analysis of key drivers, expected benefits, and the various technology options and alternatives. It also covers the 3D interposer industry players and the respective supply chain changes.
Several concurrent factors account for the growing momentum of 3D silicon and glass interposers: the continuously increasing gap between printed circuit boards (PCBs) and integrated circuits (ICs), both in terms of geometries and materials, has driven research and development of new innovative semiconductor assembly and packaging solutions over the past 10 years, including System-in-Package (SiP), Package-on-package (PoP), flip-chip Ball grid Array (fc-BGA) or more recently fan-out Wafer Level Packaging (FOWLP). Read about Research and Markets’ recent analysis on fan-out WLP at http://www.electroiq.com/index/display/packaging-article-display/8223683488/articles/advanced-packaging/packaging0/wafer-level_packaging/2010/august/new-report_on_embedded.html.
The introduction of these recent technologies fills the gap by offering finer pitch interconnections and by alleviating the external IO interface, thanks to recombined interconnections inside the package. However, a growing number of industry players now claim that the gap has become so wide that a new disruptive technology, such as 3D silicon or glass interposers, is needed, according to Yole’s findings.
Concurrently, the so-called “mid-end infrastructure” (foundries for WLP operations) has developed at an unprecedented pace over the past 3 years to meet the growing demand for wafer-level chip-scale packaging (fan-in WLCSP) and flip-chip. These new facilities, half way between front-end foundries and conventional assembly and packaging facilities, now support high-volume manufacturing on large size wafers, thus permitting economies of scale.
“These players, in search of growth opportunities, have positioned as service providers for the back-end operations for the making of TSVs and other related wafer-level assembly operations, explains Jean-Marc Yannou, project manager at Yole Développement. Thanks to 3D silicon/glass interposers, they can go one step further, and actually propose products combined with their service offer.”
Both analysts agree that the semiconductor packaging industry is not clear where 3D interposers will have the most impact. These new interposer technologies, based on silicon wafer technologies such as wafer-level photolithography, are introducing thinner and denser substrates that can profoundly change the semiconductor packaging and assembly ecosystem, notes Yole’s report. Of course, the upfront investments can sometimes limit the technology benefits.
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For each application, Yole Développement’s analysts simulate costs and compare them with projected market prices, and compare the 3D Si/glass interposer solution with existing and other emerging alternatives and derive detailed market and wafer forecasts.
Will 3D silicon/glass interposers be an intermediate step to 3D TSV in active ICs, or is this a long-term trend? How will the supply chain evolve to serve these emerging technologies? These are the questions Yole Développement addresses in this dedicated report on 3D glass/silicon interposers. Access the Yole website here: www.yole.fr. The report states which applications and uses they are likely or unlikely to support in the future, and whether these will stay niche or expand to high-volume manufacturing. Authors include Jean-Marc Yannou and Jérôme Baron.
Jean-Marc Yannou recently joined Yole Développement as technology and market expert in the fields of advanced packaging and Integrated Passive Devices. He has 15-years of experience in the semiconductor industry. He worked for Texas Instruments and Philips (then NXP semiconductors) where he served as “Innovation Manager” for System-in-Package technologies. Jérôme Baron is leading the MEMS and Advanced Packaging market research at Yole Développement. He has been involved in the technology analysis of the 3D packaging market evolution at de-vice, equipment and material supplier levels. He was granted a Master of Science degree in Micro & Nanotechnologies from the National Institute of Applied Sciences in Lyon, France.