Duke University research advances testing of 3D integrated circuits for cost-effective development of electronics

Duke University researchers are working to advance the tools and methodologies used to test 3D integrated circuits (ICs), which promise to help ensure the ongoing development of higher performance, lower power semiconductor chips.

Sponsored by Semiconductor Research Corporation (SRC), the Duke research focuses on testing of 3D integration since testing remains an obstacle that hinders mainstream adoption and mass manufacturing of 3D technology.

“Even though manufacturing processes for 3D integration are nearly mature, a barrier to technology adoption is our insufficient understanding of 3D testing issues and the need for design-for-testability (DFT) solutions,” said Krishnendu Chakrabarty, professor of Electrical and Computer Engineering at Duke. “Test challenges for 3D ICs must be addressed before high-volume production can be practical. Breakthroughs in  test technology will allow higher levels of silicon integration, fewer defect escapes, and commercial exploitation.”

The Duke research has introduced probing solutions that may enable pre-bond and post-bond testing of Through Silicon Vias (TSVs) and logic dies used in manufacturing semiconductor components. The Duke team has also introduced design-for-test (DFT) innovations for 3D stacked chip technologies.

Specifically, it is paramount to stack “known good dies” to ensure a high manfufacturing yield with stacked technology. However, due to the small feature sizes of TSVs and micro-bumps, it is extremely difficulty to probe wafers at a pre-bond stage. The Duke team has presented an innovative solution to this problem by probing multiple micro-bumps at the same time, thereby shorting TSVs and forming a TSV network. Aggregated measurements from TSV networks can then be used to detect defects in TSVs as well as in the die logic.

Furthermore, by developing the DFT structures that must be included on the die and the measurement infrastructure needed on the probe cards, the research demonstrates that the proposed approach is robust to process variations as well variations in contact resistance to the potentially non-uniform nature of probe contacts.

Next, in the area of post-bond testing, the Duke team developed a test-architecture optimization and test scheduling solution that minimizes test time by considering various stages of 3D assembly. The research included formal models based on integer linear programming as well as fast heuristic solutions. An especially innovative aspect of this research is its solution for recovering the delay overhead introduced by the DFT that is added for 3D stack testing.

“We have shown that retiming can be used to redistribute the slack on critical paths, whereby the delay overhead due to 3D DFT can be reduced to zero. This is a remarkable research breakthrough, which shows that there is something called a ‘free lunch’ after all,” said Brandon Noia, a Ph.D. student who was part of the Duke team and a recipient of the SRC Ph.D. Fellowship. Now graduated and part of SRC member company, AMD, Noia also received the European Design and Automation Association 2014 Outstanding Dissertation Award for this research.

The Duke research has already led to three U.S. patents being granted in 2014, and multiple semiconductor and electronic design automation (EDA) companies are collaborating with the Duke team on incorporating the research into their test processes—with at least one company prepared to have measurement data on chips available this fall.

“Among all EDA challenges for 3D designs, tools and methodologies for 3D stacked IC testing are critical, and this research from Duke goes a long way toward removing these obstacles,” said William Joyner, SRC director of Computer-Aided Design and Test.


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