Xilinx-on-stacked-silicon-interconnect technology

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Xilinx on stacked silicon interconnect technology

Xilinx’ (Nasdaq: XLNX) recent announcement of its stacked silicon interconnect is a play to deliver higher capacity, bandwidth, and power savings by using multiple FPGA die in a single package. It is targeted at applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance.

The technology features 3D packaging technologies, such as through-silicon vias (TSV) for its 28nm 7 series FPGAs. In an interview with Debra Vogler, senior technical editor, Liam Madden, corporate VP, FPGA development and silicon technology at Xilinx, describes the details of the silicon interposer (at 65nm technology, <1µm pitch) used in the interconnect and the yield advantages inherent in this passive approach (vs. an active approach). The side-by-side mounting of the FPGAs means there are no additional thermal issues. Additionally, the TSVs do not pass through silicon that has active devices so stress-related performance issues are avoided. Furthermore, Madden explains that the TSVs only carry power and I/O signals from the package through the interposer to the FPGA. Madden also explains that using an interposer simplifies the CAD flow.  Another unintended advantage of using the interposer is the stress relief provided to the low-k dielectric at the surface of the FPGA.

Key to the company’s success is its partnerships throughout the supply chain as well as judicious and conservative choices of technologies. In particular, TSMC’s commitment to the silicon interposer is also an important development for the industry as a whole, noted Madden.



  • Format: mp3
  • Length: 7:06
  • Size: 6.50 MB
  • Date: 11/08/10