MENT tailors products for 3D and 2.5D ICs - Advanced Packaging
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MENT tailors products for 3D and 2.5D ICs

March 30, 2011 - Business Wire -- Mentor Graphics Corporation (NASDAQ:MENT) says many of its EDA customers are designing, verifying, manufacturing and testing integrated circuit products using multi-die vertical stacking technology, 3D-IC. The company is deploying a multiple-component Tessent design-for-test product line for integrated multi-die hierarchical scan and built-in self-test (BIST) methodologies.

"3D-IC is generating a huge amount of interest and exploration because it offers an alternative to traditional scaling for achieving advances in performance, reduced power consumption, cost reduction, and increased functionality in a small package," said Walden C. Rhines, CEO and chairman of Mentor Graphics. "We're validating the use of our products for successful 3D-IC development with our leading customers who are actively working on products employing multiple die stacking approaches, including the use of interposers, or so-called 2.5D, and full 3D with through silicon vias (TSVs)."

MENT has a 3D-IC test solution, which addresses both 2.5 and full 3D test requirements, said Joseph Sawicki, vice president and general manager of the design-to-silicon division at Mentor Graphics. "At the upcoming Design Automation Conference we will talk more about our multi-die design rule checking, layout versus schematic, and extraction solutions for 3D-IC, which will address the impact of TSVs on physical verification. And, in the coming months we will describe solutions for interposer and package routing as well as product roadmaps to meet the future needs of the market."

The Tessent 3D-IC test product combines the Tessent TestKompress and Tessent LogicBIST logic test products to create highly compressed deterministic scan patterns, and on-chip-generated random patterns for high coverage in minimized test time. Low defect rates at the "known good die" stage are critical to achieving acceptable package yield in 3D-IC production. Low test time becomes even more important for 3D because die stacking may require additional test stages for partial assemblies.

Another key requirement of 3D IC is the ability to fully test the assembled multi-die structure, which presents challenges in test access and throughput. Successful testing depends on the ability to combine logic built-in self-test (LBIST), memory BIST, analog test and boundary scan test in an integrated fashion, and to distribute test commands and patterns across multiple die in a hierarchical manner. The Mentor Tessent TestKompress, Tessent LogicBIST, Tessent MemoryBIST, Tessent BoundaryScan, Tessent PLLTest and Tessent SerdesTest products work together to provide a seamless infrastructure for testing 3D structures including processor cores, logic, memory and high-speed I/O. A key advantage of the Tessent solution is the ability to reuse die-level ATPG and BIST tests at the package level. The Tessent insertion technology enables the creation of a hierarchical DFT architecture that is based on the IEEE 1149.1 standard with 3D-related enhancements such as TSV-based "test elevators." This test distribution and control architecture enables die-level patterns to be routed through multiple die after packaging. Scan patterns can target TSV interconnects by accessing scan chains on multiple die. In addition, die-targeted ATPG patterns can be retargeted to the package level with automatic pattern re-timing, allowing engineers to reuse patterns and reduce test development time.

The Tessent MemoryBIST product provides at-speed testing of stacked memory die with support for all popular DRAM protocols, and allows memory parameters (address size, waveforms) and test algorithms to be programmed post-silicon. This allows memory BIST controllers in a logic die to handle a variety of memory die stacked on top for different product variations. The product also supports at-speed testing of memory buses, which covers both bond wires and TSV interconnects. A shared-bus capability enables test of multiple memory die on the same interconnect.

Also read: LED test standards talk with Poppe, MENT

Mentor Graphics Corporation (NASDAQ: MENT) provides electronic hardware and software design products, consulting services, and support. Learn more at

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