Gate structure and 3D stacking winners will determine semiconductor industry direction - Advanced Packaging
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Gate structure and 3D stacking winners will determine semiconductor industry direction

This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.

Arthur W. Zafiropoulo, Chairman & CEO, Ultratech, Inc., San Jose, CA USA

January 11, 2011 -- Historically, companies transitioned from the 45nm node and then slipped into the 40nm node. At 32nm, they shifted into 28nm, and for 22nm, they seem to be migrating into the 20nm node. As a result, I envision the device landscape as both 20 and 22nm. For the most part, metal gate structures will be more prevalent than silicon gate structures for the 20/22nm technology node. The most interesting question is whether it will be "metal gate first" or "metal gate last." IBM is leading the metal gate first method and Intel is pushing metal gate last. It will be interesting to see the benefits of each method and which one will produce the higher yield with lower device cost. There are pros and cons to each one of these major gate structures. Work is currently being done by other companies as well, but I would say that it’s at a stage where Intel seems to have the lead for 20/22nm structures.

There will be many challenges surrounding materials selection for 22nm, which will ultimately affect yield. Also, as we see the 20/22nm structures begin to be implemented, there will be a larger percentage of those wafers packaged using flip-chip bump. There is an increase in demand for bump in a larger percentage of wafers, as the industry shifts from wire bonding to bump packaging, primarily for smart phones and tablets. As we transition from laptops to tablets, and from on-board disk drives to cloud networking, these devices will drive the transition. Companies like Apple, producing microprocessors that deliver very rich quality from its devices at a much lower cost than other dedicated microprocessor companies, also disrupt status-quo in the semiconductor industry.

For junction formation and leakage, there is a growing set of problems caused by using older technologies. As we progress to smaller features, laser annealing plays a much more important role in the structure’s performance, significantly lowering leakage. There is greater potential for laser application than there was at the 28nm or 40nm nodes. In the next couple of years, I believe that through-silicon via (TSV) for 3D stacking will increase in usage for multiple stacked chips, which will reduce cost and increase performance for tablets, smart phones, and related devices. This change will make TSV 3D stacking a strategic weapon for many chip manufacturers.

With the many technology transitions that need to occur to move to the 20/22nm node, the gate-first/gate-last debate winner will set the direction for the rest of the industry. The transition to TSV 3D will ultimately decide the winner for the balance of this decade. For certain, change is on the horizon.