Challenges in advanced wafer test probing - Solid State Technology
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Challenges in advanced wafer test probing


Overview

New semiconductor materials, alternative pad constructions, and ever-shrinking geometries are driving up the complexity and the cost of wafer test. Meanwhile, technical requirements for contact technologies are escalating and the rapid growth of 300mm wafer manufacturing is flooding wafer test areas with additional die, driving the need for innovative techniques to increase capacity and control capital equipment cost. This article surveys the trends impacting wafer test today and the industry's response to these challenges.

As Moore's Law continues to shrink device features, the rapidly increasing volume of transistors/chip creates a constant rise in the pin count/chip. High-performance computing and network devices such as microprocessors, graphics processors, network processors, and ASICs are leading the trend, requiring higher wafer test pin counts as power, ground, and input/output (I/O) pin numbers escalate. To illustrate the point, a small number of server microprocessors in production in 2003 require that >6000 pins be tested during probe, creating significant challenges for current wafer probe card technologies. New test methodologies are being developed to leverage contact technologies that enable higher parallelism and lower the cost of test (COT) while meeting the rapidly evolving technical challenges posed by trends in IC manufacturing.

High-density devices

As system on a chip (SoC) devices become prevalent in the industry, more system functionality is being supported on a single piece of silicon. Even low-end chips now come with sophisticated embedded processors, glue logic, basic analog, and embedded flash and DRAM memory. While the complexity of SoCs grows, designers are forced to steadily increase I/O interconnect pins, driving up the total pin count of each device. Despite the increase in functionality and increase in I/O needs, SoC die sizes are shrinking as process advances reduce die size faster than rising transistor counts can increase them. The combination of smaller die sizes and increased I/O requirements with the sub-130nm generation will push IC designers to fit more off-chip interconnect pads into a smaller area.

Wire-bond packaging remains the preferred packaging interconnect technology today due to its flexibility, lower cost, and the widespread infrastructure built to support it. IC designers, however, are increasingly choosing flip-chip technology to provide expanded off-chip interconnect. With a flip-chip interconnect, the interconnect bumps are placed throughout the die, not just on the periphery as with wire-bond packaging, so the die can be shrunk smaller, despite increased I/O.

Flip-chip packaging is now common in high-performance, high-power applications such as microprocessors. As other computing and networking applications increase in performance, flip-chip-style pad layouts will spread to graphics, network, and game processors. Flip-chip packages are also appearing in consumer applications that need to minimize the physical footprint.

Flip-chip packaging technology itself is evolving rapidly, progressing beyond the traditional IBM Corp. C4 processes, and no longer consists of only 250µm-pitch, high-temperature-melting (290°C), high-lead-content solder bumps. Today, the wafer test engineer faces bump pitches as low as 150µm (Fig. 1) and a variety of bump materials — including new lead-free compounds needed to meet the lead-free mandates of the European community.


Figure 1. The pitch between flip-chip bumps will continue to decline as density increases.
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Wafer probe developments

Probe card developers are working to develop flip-chip wafer probe cards that meet the challenges described above. The key to success is shrinking probe card pitches while maintaining stable contact resistance behavior, increasing current-carrying capability for high-performance devices and providing high reliability and low maintenance in high-volume production, where millions of contact cycles may be required of each probe card.

Companies are investigating a variety of approaches for advanced flip-chip probing. Manufacturers of the traditional buckling beam or COBRA-style probe cards are offering reduced pitch products, achieved by reducing wire diameter and optimizing contact properties via new pointed or wedge-shaped probe tip geometries. For example, FormFactor has introduced an approach that integrates the design of the bump-style MicroSpring contact with a specialized motion of the prober chuck that provides low contact force and stable contact performance in production

If designers choose wire-bond-type packaging, reduced die sizes and increased pin counts drive smaller bond pads at a finer pitch. Today's production wire-bond pad may be as small as 35µm ¥ 35µm at a 45µm pitch, making it difficult to control accuracy and pad damage during probing. To meet the latest pitch requirements, the contact wires used by traditional probing technologies must become smaller. Smaller wires, however, are more fragile and consequently more prone to mechanical damage, and have difficulty carrying the currents required by high-performance designs.

Fine-pitch wire-bond pads also make it difficult to achieve sufficient contact force — to break through the oxidation layer on the contact surface — without inflicting excessive damage on the pad structure. As the wire-bond pad surface shrinks, the proportional amount of damage from traditional probing techniques increases. Compounding the problem, cantilever needle probe tips tend to shift slightly as the card is used, and may eventually create scrub damage that encroaches on the pad or bump edge's keep-out zone. With a smaller zone to hit, it gets harder to contain the damage within an acceptable area. As a result, IC manufacturers using cantilever needle probe cards are often forced to rely on expensive optical inspection tools to examine pad damage, appreciably adding to the COT.

Probe card manufacturers are developing MEMS-type probing structures to address the challenges of probing fine-pitch wire-bond pads, combining fine-pitch capabilities, mechanical stability, low probe force, and controlled pad damage. While improved epoxy-type cantilever probe cards are still the leading solution for fine-pitch probing, MEMS-type structures will become more common in wire-bond probing as high-volume production shifts to sub-60µm wire-bond pad pitch.

Growing need for known good die

Multichip packages (MCPs) are rapidly gaining popularity in smaller, thinner, feature-packed consumer products such as next-generation mobile phones. In order to maintain acceptable yield and cost levels, MCP manufacturers require known good die (KGD) that have been fully verified before they are packaged.

One intriguing example of development in the MCP is the 3-D multichip structure with two-die stacked CSP (S-CSP), which produces silicon efficiencies approaching 200%, largely for Flash-SRAM memory combinations. Many cell phones have two S-CSP devices to accommodate their memory requirements, but emerging and next-generation cell phones are substantially more complex and require additional memory capacity for code and data storage. In response to this need, three- and four-die stack extensions with silicon efficiencies >300% are in development and will be driven rapidly into high-volume use.

Customers receiving KGD typically have stringent requirements for pad damage to ensure reliable wire-bonding during packaging. Wire-bond process yield and reliability for MCPs may be sensitive to probe-induced pad damage. Vertical manufacturers who design, manufacture, and package their own devices can manage pad damage due to probing in order to achieve a balance between probe performance and packaging yield. But when a supplier tests wafers for KGD, control of pad damage becomes a critical specification, as customers cannot accept any possibility of packaging yield loss due to probe damage. Even if the customer rejection rate due to pad damage is as low as 1%, it can mean literally millions of dollars in lost revenues to the chip manufacturer.

Although the demand for KGD is mainly focused on SRAM and flash devices, the pressure is building for more final test at wafer for all types of ICs. As KGD testing moves to high-frequency, high-performance devices, probe card technologies that support multi-GHz final test-level accuracy will be required. Instead of waiting to test devices until the backend assembly process, where it is much more expensive to identify faulty chips, manufacturers can migrate more of the testing to the frontend whole-wafer level. This would reduce the time and expense required to weed out defective chips by using wafer probe test to provide greater levels of device validation.

Probe cards that provide controlled pad damage through low contact force and consistent scrub characteristics are available for KGD-probing applications. A variety of probe card solutions can be found for high-speed, high-fidelity KGD probing, including single-DUT, RF-capable probe cards to multi-DUT, and 500Mhz probe cards used for graphics DRAM final test on the wafer (Fig. 2).


Figure 2. New probing technologies provide the precision placement and low probing force needed for smaller, more delicate geometries in advanced logic devices.
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New materials

Another trend impacting the wafer test area is the widespread adoption of new materials in advanced IC manufacturing — low-k dielectrics and copper, principally at the 130nm process node and below. As frequency increases, low-k dielectrics with permittivities midway between those of silox and air offer a good compromise in achieving acceptable electrical performance. These critical low-k interlayer dielectrics (ILDs) typically achieve improved electrical characteristics by providing a structure of microscopic air bubbles trapped in a glass or polymer material, and, consequently, have a resistance to cracking and structural failure that is one order of magnitude lower than traditional dielectrics.


Figure 3. Deformation of features with low-k dielectrics due to high-force probing. (Figure courtesy of Motorola)
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The fragile nature of low-k dielectrics is an added hurdle for wafer probing and packaging. Low-k and ultra-low-k (ULK) ILD materials used in advanced 90nm IC manufacturing require probing techniques that can do their job without deforming or damaging the dielectric or structures beneath them (Fig. 3). This is crucial for bump probing because the contacts are almost always placed over active circuits. Even with peripheral pads, designers are starting to move the active circuitry out under the pads themselves to accommodate higher-density designs.

The fragile low-k challenge creates a unique constraint for probe technology; typically, stable contact resistance and long probe lifetime is achieved by building a high-force probe. Low-k dielectrics can no longer tolerate traditional high-force probing methods, so new approaches that combine low contact force with stable contact resistance and long-lifetime probes are needed.

The use of copper for high-performance circuitry in the 130nm range and below also creates new challenges when probing. To minimize process steps and reduce cost, manufacturers would prefer to use copper as the bond pad material. Copper, however, oxidizes aggressively. The oxide creates difficulties at probe and in the wire-bond process, so most manufacturers are capping copper pads with aluminum to ensure stable probing and wire-bonding processes.


Figure 4. With aluminum-clad copper structures, the probing process needs to be carefully optimized to create an acceptable process window to achieve sufficient contact resistance and minimal copper exposure.
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The ideal probing solution for an Al/Cu stack preserves the copper encapsulation because it does not penetrate the aluminum cap all the way to the underlying copper. Penetration of the Al cap is a function of contact pressure and probe mechanics (Fig. 4). Limiting Al cap penetration requires reducing contact pressure, but still maintaining acceptable electrical contact performance. The trade-off between contact performance and contact pressure narrows the probe process window, and is leading many manufacturers to examine the complete probe process to reduce variation induced by the probe card, prober, and wafer characteristics.

300mm wafer test challenges

Along with shrinking geometries, KGD, and new semiconductor materials, the wafer test floor is coping with moving to 300mm wafer test. A 300mm wafer costs 130% more to produce than a 200mm wafer, but has as many as 2.5¥ the number of die/wafer. Test costs/die do not scale down as die costs do with larger wafers. Total test costs increase if significant improvements in the test process are not made.

For example, if test costs are 12% of a 200mm wafer's manufacturing cost, they will increase to 20% for 300mm due to the increased unit volume of die available. Test costs may even be higher, because 300mm yields are higher, and it takes longer to test good die than bad. This is complicated by the fact that test times/die are increasing due to the complexity of next-generation IC designs.

The most effective method to control the 300mm wafer cost of test is to increase the number of devices that are tested in parallel. Parallelism is a well-established technique for memory test, with up to 256 die being tested in one touchdown of the prober. At the theoretical limit, a 256-die in-parallel probe card can provide 8¥ the throughput of the standard X32 probe card in use in 200mm fabs, reducing the total number of testers needed for wafer test by a factor of eight. A 30,000 wafer start/month 200mm wafer test floor that requires 50 32-in-parallel testers can be compared to a 30,000 wafer starts/month, 300mm wafer test floor that only requires 16 new 256 in-parallel testers to provide 2.5¥ the die output of the 200mm fab.

As built-in-self-test and design-for-test methodologies evolve in the nonmemory arena, parallel test will increase. High-parallelism test will require probe cards with higher pin counts, but capable of supporting small pad pitches with minimal pad damage. Finally, increased parallel wafer test requires close coordination between test methodologies, test hardware, and wafer test probe card design.

Conclusion

Wafer probing will need to evolve to accommodate the many trends affecting IC manufacturing today. At the same time, COT must continue to decline to ensure test does not become the limiting economic factor in producing next-generation devices. It is imperative that wafer probes adapt to the industry roadmap for reduced contact sizes and pitches, while ensuring reliable contact without threatening the structural integrity of the IC contacts and underlying circuitry.

Promising advances in wafer-probing technology and techniques give reassurance that wafer probing is rising to emerging challenges. New technologies that are moving beyond traditional wire probing based on cantilever or buckling-beam vertical probe structures will offer improved electrical performance, higher-precision probe placement, coupled with reduced probe force to minimize pad damage. Because the probes are arranged in an array, they can support extremely fine-pitch contacts that can number in the thousands to improve wafer test throughput, and thereby lower test costs. In addition, the superior signal integrity supports greater functional test at the wafer level, paving the way toward final test at wafer.

Mark Brandemuehl, FormFactor Inc., Livermore, California

Mark Brandemuehl is VP of marketing at FormFactor Inc., 2140 Research Drive, Livermore, CA 94550; ph 925/456-3904, fax 925/294-8147, [email protected]

 

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