3D integration comes in many flavors for semiconductor industry, says CEA-Leti chief scientist - Advanced Packaging
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3D integration comes in many flavors for semiconductor industry, says CEA-Leti chief scientist


By Debra Vogler, senior technical editor

February 2, 2011 -- Simon Deleonibus, IEEE Fellow, CEA Research Director, and Chief Scientist at Leti sat down at IEEE’s International Electron Devices Meeting (IEDM 2010 12/6-12/8/10, San Francisco, CA) with Debra Vogler, senior technical editor, to give his view of industry research trends and looks ahead to next year’s event.

Listen to Deleonibus' interview: Download (iPod/iPhone users)  or Play Now

Deleonibus observes that all the major semiconductor industry players are embracing 3D integration in different "flavors." This will allow the industry to relax the constraint of IC scaling -- necessary in part because lithography is not yet ready for aggressive scaling.

New applications are also coming out using heterogeneous integration, especially the mixing of memory and logic, and possibly passive devices and others that are not CMOS-based (e.g., sensors, actuators). Leti is very active in thin film technology and fully depleted silicon-on-insulator (FDSOI), and Deleonibus observes that these technologies are also being evaluated by an increasing number of companies. He believes new applications will emerge because of the flexibility and advantages of wafer bonding. 

Looking ahead, Deleonibus says that through-silicon via (TSV) technology has to mature. While there are many advantages to using TSVs, issues such as isolation and strain-induced effects from TSVs will require innovation to resolve. He mentions that stress-free innovations, such as carbon nanotubes (CNTs) or other stress-free solutions using atomic layer deposition (ALD) or different flavors of chemical vapor deposition (CVD) processes, may be of interest.

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