IFTLE 132 2012 IEEE IEDM: IBM, RPI, Tohoku Univ and TSMC ; Wide IO Memory

By Garrou

Several papers at the  Dec 2012 IEEE IEDM meeting were of 3D interest.

Subu Iyer of IBM addressed the evolution of high end memory + logic systems.

With the wider utilization of multicore processors and the need for even larger amounts of  cache, Subu expects cache-processor stacks to proliferate. The figure below shows 3D integrated eDRAM die. The aspect ratio of the TSV in the thinned die is <10:1 .="" a="" across="" and="" appropriate="" are="" as="" at="" chip-to-chip="" chose="" contact="" dimension="" dimensional="" fat="" few="" for="" hierarchy="" higher="" ibm="" incongruity="" integrate="" interconnects="" levels="" microns="" minimize="" nm.="" o:p="" of="" reasons:="" respect="" several="" tens="" the="" to="" tsvs="" two="" upper="" wire="" with="">
Die may be attached face to face or face to back which  allows for multi die stacking. The stacking process is very sensitive to die warpage and the handling of thin die and controlling their warpage is reportedly one of the key challenges.

Fully Packaged, Fully Functional eDRAM on a Logic face-to-face Die Stack on Organic Laminate fabricated in IBMs 32nm process

James Lu of RPI reported on a novel partition and assembly approach that combines both the electromagnetic (EM) and analytical simulations to accurately model and analyze several through-silicon-via (TSV) based 3D power delivery networks, which are composed of various stacked-chips,
interposer, and package substrate.

Tohoku Univ

A serious potential reliability issue is the local deformation produced in the stacked LSI die with respect to the die thickness and the sub-surface structures formed after stress-relief methods. From electron backscatter diffraction (EBSD) analysis, more than one degree (>1°) of local misorientation is created in the stacked chip around μ-bump region. This induces a large tensile stress above the μ-bump region and relatively small compressive stress in the bump-space region, which leads to an enhancement in the n-MOSFET mobility in the μ-bump region and decrease in mobility at bump-space region.
Due to the very large CTE difference between In and Si vs Cu and Si, InAu μ-bumps induce a huge amount of tensile stress (> 300 MPa) in the stacked die even at bonding temperature as low as 200C

Even after 500 cycles of temperature cycles , a 20 μm dia Cu-TSV array on 40- μm pitch induces -570 MPa of compressive stress and a large variation in the induced stress values between different TSVs in the same array. For the LSI die/wafer thickness of anything less than 50 μm, the Young modulus and hardness of the thinned die no longer behaves like a bulk single crystal Si, which severely increases the reliability risks in the highly integrated 3D-LSIs.

In another Tohoku / ASET collaboration they studied “Characterization of Chip-level Hetero-Integration Technology for High-Speed, Highly Parallel 3D-Stacked Image Processing System”. A CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, were processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking.


TSMC reported on “Thinning, Stacking, and TSV Proximity Effects for Poly and High-K/Metal Gate CMOS Devices in an Advanced 3D Integration Process”. Poly and High-K/Metal Gate (HKMG) CMOS wafers were successfully thinned and stacked, showing little to no degradation in the process.
The variations in electrical behavior due to thinning for PMOS and NMOS of Poly Gate devices are less than 2%; for HKMG devices, the variations are less than 1.7%. The device characteristics are preserved after the thinning process.

The chip-on-wafer (CoW) stacking process is found to have little effect on device performance. The Id-Vd and Id-Vg characteristics for PMOS and NMOS are found to have little to no degradation in stacking process. The power and time delay trade-offs of ring oscillators show comparable performances before and after the stacking process .

The TSV induced mechanical stress can affect the device performance. Both the experiment and simulation results show that ΔIdsat of HKMG is smaller than Poly Gate in both p- and n-channel MOSFETs as shown below. For PMOS, the ΔIdsat of HKMG device is around 0.3 times when normalized to Poly Gate device; for NMOS, the ratio is about 0.4 – 0.5.


ΔIdsat for HKMG device is proportional to TSV diameter square, independent of TSV orientation, device polarity, and device distance from TSV.
They conclude that the impact of wafer thinning, stacking, and TSV proximity effects to Poly and HKMG CMOS devices are analyzed. Little to no degradation to device performance due to TSV manufacturing demonstrates successful integration of state-of-the-art CMOS technology. This work provides essential information for future 3DIC integration.

Wide IO Memory Applications
For those of you interested in the difference between future high performance memory and mobile memory, Sitaram Arkalgud of Sematech has put together a nice slide addressing the differences

For all the latest on 3DIC and advanced packaging stay linked to IFTLE……………..


Dr. Phil Garrou gives his insight into leading edge developments in 3-D integration and advanced packaging, reporting the latest technical goings on from conferences, conversations, and more.

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