Deposition: Pentacene organic thin-film transistors and ICs - Solid State Technology
This article is from

Deposition: Pentacene organic thin-film transistors and ICs

Hagen Klauk, Thomas N. Jackson,* Center for Thin Film Devices and Electronic Materials and Processing Research Laboratory, The Pennsylvania State University, University Park, Pennsylvania

Using the organic semiconductor pentacene as the active material, we have fabricated high-performance organic thin-film transistors and the fastest ICs using organic transistors reported to date. We have also developed a low-cost manufacturing technology for organic/ inorganic complementary circuits based on hydrogenated amorphous silicon n-channel thin-film transistors and pentacene p-channel transistors.

Organic thin-film transistors (TFTs) have made impressive progress over the past decade, and it appears increasingly likely that organic TFTs will find use in a number of low-cost, large-area electronic applications. Such applications may include active matrix liquid crystal flat panel displays (FPDs), active matrix all-organic emissive FPDs, active matrix imagers, smart cards, smart price and inventory tags, and large-area sensor arrays.

Organic TFTs provide two principal advantages over TFTs based on inorganic semiconductors — they can be fabricated at lower temperature and, potentially, at significantly lower cost. Low process temperatures, in particular, may allow organic TFTs to be integrated on inexpensive plastic substrates rather than glass. The prospect of flexible, unbreakable, extremely low-weight FPDs at relatively low cost has spurred a number of manufacturers and government agencies to consider plastic displays, imagers, and detectors for a variety of military, medical, industrial, and consumer applications. Organic TFTs may also allow simple ICs to be fabricated at extremely low cost for applications such as RF price labels, identification tags, and smart cards.

Since many organic semiconductors have p-type conductivity, they can also be used in a complementary IC technology combining n-channel hydrogenated amorphous silicon TFTs with p-channel organic TFTs. Complementary thin-film IC technology, analogous to silicon CMOS, is of particular interest for portable applications where low power consumption is important.

The performance of organic TFTs has improved dramatically since such devices were first demonstrated in 1983 [1-7], and optimized organic TFTs now show electrical characteristics approaching or exceeding those of hydrogenated amorphous silicon TFTs. For example, carrier field-effect mobilities as large as 2.2cm2/V-sec have been obtained in organic TFTs that use the small-molecule, polycyclic, aromatic hydrocarbon pentacene as the active material [8]. In addition to large carrier mobility, a large on/off current ratio is required for TFTs to be useful as pixel-addressing devices in active matrix displays and imagers. Small TFT subthreshold slope and near-zero threshold voltage are also important to reduce the power consumption of an IC or display. Finally, to address organic light emitters in an all-organic emissive display, TFTs must be able to drive fairly large drain currents [9].

Device fabrication

Click here to enlarge image

Figure 1. Schematic cross section of a pentacene thin-film transistor on a glass substrate.

We have fabricated pentacene TFTs and pentacene ICs on borosilicate glass (Corning 7059) and on inexpensive plastic substrates using the device structure shown in Fig. 1. Nickel was used for the gate electrodes; silicon dioxide was deposited to form the gate dielectric layer; and palladium was used for the source and drain contacts. The relatively large work function of palladium is expected to improve carrier injection into the organic semiconductor. To form the active TFT layer, the pentacene was thermally evaporated in vacuum at a pressure near 10-5Pa with a deposition rate near 1Å/sec. During the pentacene deposition, the substrate was held at 60°C to improve molecular ordering in the pentacene film, which leads to larger carrier mobility and better device characteristics [10].

Click here to enlarge image

Figure 2. Atomic force microscopy (AFM) images of pentacene films deposited onto: a) thermally grown silicon dioxide; b) ion-beam-sputtered palladium; c) thermally evaporated palladium; and d) ion-beam-sputtered silicon dioxide.

Molecular ordering also benefits from a smooth substrate. This is illustrated in Fig. 2a, which shows an atomic force microscopy (AFM) image of a 400Å-thick pentacene film deposited onto the smooth surface of an oxidized silicon wafer. The thermally grown silicon dioxide has a peak-to-valley roughness of 8Å and an RMS roughness of 1Å, and the deposited pentacene film shows good molecular ordering with large, micron-sized grains. For comparison, Fig. 2c shows an AFM image of a pentacene film deposited onto the significantly rougher surface of evaporated palladium. The evaporated palladium film has a peak-to-valley roughness of 48Å and an RMS roughness of 5.4Å, and the deposited film shows very little ordering.

The nickel gate electrodes, the silicon dioxide gate dielectric layer, and the palladium source/drain contacts were all prepared by ion-beam sputtering to obtain a smooth gate dielectric and smooth source/drain contacts. We have found that ion-beam-sputtered metal and dielectric films have exceptionally smooth surfaces, leading to improved molecular ordering in the deposited pentacene layer. Figure 2b shows an AFM image of pentacene deposited onto ion-beam-sputtered palladium. The ion-beam-sputtered palladium has a peak-to-valley roughness of 11Å and an RMS roughness of 1.3Å, and the deposited pentacene film appears well ordered, with terraced, micron-sized grains. Ion-beam-deposited SiO2 films are quite smooth as well, with a peak-to-valley roughness of 20Å and an RMS roughness of 2Å. Figure 2d shows that when pentacene is deposited onto the smooth surface of our ion-beam-deposited SiO2 gate dielectric layer, an active TFT layer with excellent molecular ordering is obtained.

Silicon dioxide gate dielectric layers were prepared in an Oxford ion-beam deposition system by sputtering from a single-crystal silicon target in a partial pressure of oxygen. The process pressure was 0.1Pa, with an oxygen partial pressure of 0.075Pa and an argon partial pressure of 0.025Pa. To reduce the mechanical film stress often observed in sputtered dielectric films, substrates were held at a temperature of 80°C during deposition.

The refractive index of ion-beam-deposited SiO2 films is nearly identical to that of thermally grown silicon dioxide. To evaluate the electrical properties of ion-beam-deposited silicon dioxide, MOS capacitors were fabricated by depositing SiO2 onto lightly doped single-crystal silicon substrates and evaporating aluminum contacts through a shadow mask. Prior to the dielectric deposition, the silicon substrates underwent a standard cleaning procedure using NH4OH:H2O2:H2O, HCl:H2O2:H2O, and HF:H2O solutions.

Measurements of the high-frequency (100kHz) C-V characteristics of a MOS capacitor fabricated using a 630Å-thick ion-beam-deposited SiO2 film on single-crystal silicon indicate that the flatband voltage shifts by about 6V upon thermal treatment at 150°C without gate bias stress. When the capacitor is stressed at 5MV/cm and 150°C for several hours, the flatband voltage shifts by about 6V with a positive gate potential, and by about 2V with a negative gate potential. Thus, the total flatband voltage shift during thermally assisted gate bias stress is 8V, indicating an oxide charge density of 3 x 1012cm-2. Although this is two or three orders of magnitude larger than the oxide charge density of high-quality thermally grown silicon dioxide, it is sufficiently low for the purpose of fabricating organic TFTs. The properties of the deposited oxide films can be further improved by annealing at elevated temperature. The inversion characteristics measured at low frequency (10kHz) under strong illumination improve after a 30 min/500°C anneal in forming gas. Ion-beam-deposited SiO2 films also have large electrical resistivity near 2 x 1013W-cm. Dielectric breakdown occurs when the electric field exceeds 8MV/cm, somewhat lower than the breakdown field of thermally grown silicon dioxide films.

Among the challenges of fabricating organic TFTs based on small-molecule materials like pentacene is patterning of the organic active layer. Although these materials are often not attacked in a bulk sense when exposed to the solvents commonly used in photolithographic processes, the electrical characteristics of devices tend to degrade significantly. If the active TFT layer cannot be patterned, current leakage between circuit or display elements can be a significant problem, unless the threshold voltage can be controlled so that the active layer is normally nonconducting.

Although pentacene is an excellent insulator, with resistivity around 1014W-cm, evaporated pentacene films have a tendency to form a carrier accumulation channel at the substrate interface, and a positive gate voltage is often necessary to deplete the channel. As a result, current leakage through an unpatterned active layer can be significant. To reduce the leakage between individual TFTs, we have employed a Corbino transistor layout in which the source electrode forms a closed ring around the active TFT area, with the drain electrode located in the center. For a discrete device, this allows a patterned gate to control the entire current path from source to drain electrode. Figure 3a shows a photograph of a Corbino-type pentacene TFT.

Discrete pentacene TFTs *** Figure 3b shows electrical characteristics of a Corbino-type pentacene TFT fabricated on glass with a gate length of 5µm, a gate width of 500µm, and a gate dielectric thickness of 1400Å. The saturation field-effect mobility of this device is 1.7cm2/V-sec, to our knowledge the largest carrier mobility reported for organic transistors fabricated on a substrate other than single-crystal silicon. The on/off current ratio for this device is 108, and the off-current is near the noise level of the test setup used, indicating low leakage due to the Corbino layout of the device. Devices with an open electrode configuration fabricated on the same die had off-currents in the nanoamp range.

Click here to enlarge image

Figure 3. a) Photograph and b) electrical characteristics of a Corbino-type pentacene TFT with a gate length of 5µm and a gate width of 500µm.

For organic TFTs to be useful for all-organic, active matrix emissive FPDs, they must be able to drive fairly large currents in order to produce bright emission from organic light-emitting diodes (LEDs). We showed that even modest-sized pentacene TFTs (a footprint area of about 10-4cm2) can drive several milliamps of drain current. The available drive current is substantially larger than that required to drive an organic LED pixel. For a typical organic LED with a pixel area of about 10-3cm2, the expected drive current is on the order of 10µA [11, 12]. Using the layout rules of the transistor described here, this would require only about 10-5cm2 footprint area, or about 1% of the pixel area. Low power consumption is an essential prerequisite for many potential organic TFT applications, and devices with low subthreshold slope and near-zero threshold voltage are desirable. Using the fabrication process described above, we have obtained pentacene TFTs on glass substrates with subthreshold slope as low as 0.4 V/decade, to our knowledge the lowest subthreshold slope reported for organic TFTs. Obtaining low or near-zero threshold voltage with pentacene TFTs is more difficult, and we are thus far unable to control threshold voltage reliably for pentacene TFTs. For example, the device shown in Fig. 3 has a threshold voltage of 10V.

Click here to enlarge image

Figure 4. a) Photograph and b) electrical characteristics of pentacene TFTs fabricated on a flexible, transparent, polyethylene terephthalate (PET) film.

To demonstrate the potential of organic TFTs for low-cost electronic applications, we have fabricated pentacene TFTs on inexpensive, flexible plastic substrates. Figure 4a shows a photograph of pentacene devices fabricated on a flexible, transparent polyethylene terephthalate (PET) film. Since handling of thin, flexible plastic films during device processing is often complicated by problems related to film warpage and poor thermalcontact, the 50µm-thick PET film was mounted to a glass carrier using a 200µm-thick polyethylene adhesive layer prior to device fabrication. After device fabrication, the plastic film was simply peeled off the glass carrier. The maximum process temperature was kept below 100°C to reduce substrate shrinkage.

Click here to enlarge image

Figure 5. a) Photograph of a pentacene inverter with an integrated level-shift stage and b) schematic diagram and voltage transfer characteristics.

Also shown in Fig. 4b are the electrical characteristics of a pentacene TFT with a gate length of 44µm, a gate width of 240µm, and a gate dielectric thickness of 1700Å. The device has a carrier mobility of 1.1cm2/V-sec, an on/off current ratio near 103, and a threshold voltage of 2V. To our knowledge, the carrier mobility is the largest reported for organic TFTs on flexible substrates.

Pentacene ICs

By integrating two transistors in a circuit configuration such that one of them is acting as a voltage-controlled switch (or driver) and the other as an active load, a simple voltage inverter can be made. However, two problems need to be addressed before useful ICs based on pentacene TFTs can be fabricated. When used in a circuit layout, the Corbino TFT structure shown in Fig. 3 must be modified so that the drain electrode located in the center can be addressed. However, we have found that adding a metal line to contact the drain electrode introduces unacceptable current leakage if the pentacene active layer is left unpatterned. We have therefore applied a simple double-layer resist active-layer patterning technique that does not require the organic film to be exposed to process chemicals. Before the pentacene layer is deposited, the substrate is coated with a layer of polymethylmethacrylate (PMMA), followed by a layer of novolac-based photoresist. After baking the resist, near-UV exposure through a mask is used to define the active areas in the novolac layer. The pattern is then transferred to the PMMA layer using a flood deep-UV exposure during which the novolac layer acts as a conformable mask. Finally, the PMMA is developed in toluene to open the active device areas. By optimizing the exposure and development process for both layers, a re-entrant double-layer profile is created [13]. When the pentacene is deposited, the active layer breaks along the resist edges to leave isolated device areas and eliminate current leakage in the pentacene film outside the active device areas.

Click here to enlarge image

Figure 6. a) Schematic cross section, b) voltage transfer characteristics, and c) transition current as a function of input voltage of a complementary a-Si:H/pentacene inverter.

A second problem arises from the fact that our pentacene TFTs often have positive threshold voltage, and thus a simple enhancement-mode circuit layout will not typically yield useful inverter operation. When using TFTs with a positive threshold voltage, the circuit showed usefully large voltage gain, but the input and output levels were not compatible due to the positive threshold voltage of the drive TFT.

To adjust the logic levels so that they correspond properly to the on-and-off states of the drive TFT, we have integrated a level-shift stage with each logic gate. The level-shift stage requires two additional TFTs that act as saturated loads in a voltage divider configuration. An additional power supply (the level-shift bias) is used to adjust the output of the level-shift stage, thus allowing inverter operation over a wide range of threshold and supply voltages. The schematic diagram and the voltage transfer characteristics of a depletion-mode inverter circuit on glass with integrated level-shift stage are shown in Fig. 5a, and a photograph of the circuit is shown in Fig. 5b. The inverters have a driver gate length of 5µm, a driver gate width of 800µm, a load gate length of 30µm, and a load gate width of 300µm. The inverter supply bias is -60V, and the level-shift bias is +50V. Large voltage gain is obtained, and the input and output levels are compatible. Using inverters with integrated level shifting we have fabricated 5- and 7-stage ring oscillators on glass substrates. These circuits function over a wide range of supply and level-shift voltages, and we have measured propagation delays as low as 73µsec per stage. The propagation delay in our pentacene ring oscillators is not limited by the intrinsic inverter speed, but by the low current level chosen for the level-shift stage. To estimate the intrinsic inverter speed, we have used a 200kHz pulse generator to drive a pentacene inverter with no level-shift stage directly. The rise and fall time constants — extracted from the inverter output by fitting exponential functions to the output waveform — are 0.5µsec and 0.3µsec, respectively.

Complementary a-Si:H/pentacene ICs

Although hydrogenated amorphous silicon has ambipolar transport characteristics and can be operated in both p- and n-channel mode [14], p-channel a-Si:H TFTs have inferior characteristics compared with n-channel devices, and complementary ICs using only a-Si:H transistors have not demonstrated useful performance. Most organic thin-film semiconductors, by contrast, operate only in p-channel mode, although a small number of n-type organic semiconductors have been identified and all-organic complementary ICs have recently been demonstrated [15].

We have developed a low-cost manufacturing process for complementary inorganic/organic ICs using hydrogenated amorphous silicon n-channel TFTs and pentacene p-channel TFTs [16]. Circuits were fabricated on borosilicate glass (Corning 7059) using an inverted-staggered tri-layer structure for the a-Si:H devices [17] and a pentacene TFT device structure similar to that shown in Fig. 1.

These complementary circuits show large voltage gain, excellent logic-level conservation, and low static power dissipation (see Fig. 6). Using 5- and 11-stage ring oscillators, we have measured propagation delay as low as 5µsec/stage and power dissipation as low as 0.2µW/stage. To our knowledge, these are the fastest ICs using organic transistors reported to date.


Organic TFTs with electrical characteristics similar to or better than those typically obtained with hydrogenated amorphous silicon devices have been demonstrated on glass substrates and on inexpensive flexible plastic substrates. In addition to lower process temperatures, organic TFTs may offer significantly lower manufacturing costs compared with a-Si:H technology. Potential applications for organic TFTs, all-organic integrated TFT circuits, and complementary inorganic/organic TFT circuits are in a variety of large-area, low-cost electronic, and optoelectronic applications.


Additional authors of this article include David J. Gundlach, Jonathan A. Nichols, Chris D. Sheraw, and Mathias Bonse.

The work was supported by the Defense Advanced Re-search Projects Agency (DARPA), Sarnoff Corp., and Opticom ASA.


  1. F. Ebisawa, T. Kurokawa, S. Nara, "Electrical Properties of Polyacetylene/Polysiloxane Interface," J. Appl. Phys., Vol. 54, pp. 3255-3259, 1983.
  2. A. Tsumura, H. Koezuka, T. Ando, "Macromolecular Electronic Device: Field-effect Transistor with a Polythiophene Thin-film," Appl. Phys. Lett., Vol. 49, pp. 1210-1212, 1986.
  3. J.H. Burroughes, C.A. Jones, R.H. Friend, "New Semiconductor Device Physics in Polymer Diodes and Transistors," Nature, Vol. 335, pp. 137-141, 1988.
  4. G. Horowitz, D. Fichou, X. Peng, Z. Xu, F. Garnier, "A Field-effect Transistor Based on Conjugated Alpha-sexithienyl," Solid State Comm., Vol. 72, pp. 381-384, 1989.
  5. F. Garnier, R. Hajlaoui, A. Yassar, P. Srivastava, "All-polymer Field-effect Transistor Realized by Printing Techniques," Science, Vol. 265, pp. 1684-1686, 1994.
  6. J.G. Laquindanum, H.E. Katz, A.J. Lovinger, A. Dodabalapur, "Morphological Origin of High Mobility in Pentacene Thin-film Transistors," Chem. Mater., Vol. 8, No. 11, pp. 2542-2544, 1996.
  7. Y.Y. Lin, D.J. Gundlach, S.F. Nelson, T.N. Jackson, "Stacked Pentacene Layer Organic Thin-film Transistors with Improved Characteristics," IEEE Electron Device Lett., Vol. 18, No. 12, pp. 606-608, 1997.
  8. D.J. Gundlach, C.C. Kuo, S.F. Nelson, T.N. Jackson, "Organic Thin-film Transistors with Field-effect Mobility >2 cm2/V-sec," 57th Device Research Conference Digest, pp. 164-165, 1999.
  9. G. Gu, S.R. Forrest, "Design of Flat-panel Displays Based on Organic Light-emitting Devices," IEEE J. Sel. Topics Quant. Electr., Vol. 4, pp. 83-99, 1998.
  10. D.J. Gundlach, Y.Y. Lin, T.N. Jackson, S.F. Nelson, D.G. Schlom, "Pentacene Organic Thin-film Transistors — Molecular Ordering and Mobility," IEEE Electron Device Lett., Vol. 18, No. 3, pp. 87-89, 1997.
  11. H. Sirringhaus, N. Tessler, R.H. Friend, "Integrated Optoelectronic Devices Based on Conjugated Polymers," Science, Vol. 280, pp. 1741-1744, 1998.
  12. A. Dodabalapur et al., "Organic Smart Pixels," Appl. Phys. Lett., Vol. 73, pp. 142-144, 1998.
  13. B.J. Lin et al., "Practicing the Novolac Deep-UV Portable Conformable Masking Technique," J. Vac. Sci. Technol., Vol. 19, pp. 1313-1319, 1981.
  14. G.W. Neudeck, K.Y. Chung, "A CMOS-like Ambipolar a-Si:H TFT Inverter Circuit," Proceedings of the SID, Vol. 28, pp. 397-401, 1987.
  15. Y.Y. Lin et al., "Organic Complementary Ring Oscillators," Appl. Phys. Lett., Vol. 74, pp. 2714-2716, 1999.
  16. M. Bonse et al., "Integrated a-Si:H / Pentacene Inorganic/Organic Complementary Circuits," IEDM Tech. Dig., pp. 249-252, 1998.
  17. D.B. Thomasson, T. N. Jackson, "High-mobility Tri-layer a-Si:H Thin-film Transistor with Ultra-thin Active Layer," IEEE Electron Device Lett., Vol. 18, pp. 397-399, 1997.

For more information, contact Hagen Klauk at the Center for Thin Film Devices and Electronic Materials and Processing Research Laboratory, The Pennsylvania State University, University Park, PA 16802; ph 814/865-1267, fax 814/865-7065, e-mail [email protected]


Recent Semiconductors News

Solid State Technology Article Categories:

Semiconductors Materials
Industry News Subsystems
Wafer Processing Facilities
Lithography Wire News
InspectionSST Magazine Current Issue
Device ArchitectureSST Archives