GLOBALFOUNDRIES Takes a Different Approach to HKMG in AMD’s Llano CPU/GPU
As a processor, it garnered pretty favorable reviews, but of course we were keen to get it into the lab and see how it had been put together. When we did, it became a bit of a mystery -- we couldn't see any significant differences in gate stack between NMOS and PMOS! It's common wisdom that you need different work function materials in the NMOS and PMOS gates to differentiate them and make up the CMOS circuitry.
For example, Panasonic uses lanthanum to tweak the work function of their NMOS transistor and distinguish it from the PMOS stack in their HKMG Uniphier chip that we looked at back in the spring.
Fig. 1 Panasonic 32-nm HKMG Transistor
When we look at the Llano, it also uses a gate-first transistor style, with TiN as the gate metal, but there the resemblance stops. Below (Fig. 2) is a composite image of the Llano NMOS/PMOS transistors, and you can see that they are more complex.
Fig. 2 AMD/GloFo 32-nm HKMG NMOS and PMOS Transistors
The NMOS and PMOS gate stacks shown in Fig. 3 appear to be the same -- highly silicided poly on a thin AlO barrier layer, on TiN gate metal, which is on the Hf-based hi-k layer with a SiO interfacial layer on the substrate. The AlO layer in the PMOS stack is more diffuse, and some of the aluminum has migrated into the TiN, and arsenic is present as expected in the NMOS, but essentially they are the same.
Fig. 3 AMD/GloFo Transistor Gate Stacks
The extra thickness in the SOI is the clue to what we think is going on in this part. The extra thickness is actually a layer of epitaxial SiGe, which changes the relationship with the gate metal and shifts the Vt, instead of using a dopant in the hi-k. Some work was done on this topic at SEMATECH a few years ago , and of course AMD and IBM were members and would have received the results.
The schematic in Fig 4 shows conceptually what happens; the valence band of the substrate is shifted because of the Ge, and also due to the compressive strain applied by the embedded SiGe source/drain and the nitride stress layer.
Fig. 4 Schematic of Band Diagram for Transistor with SiGe Channel 
Fig. 5 Drive Current Improvement in SiGe-Channel Device
In fact, SEMATECH's ESSDERC paper from 2005  agrees nicely with what we see in the AMD and Intel parts. The Llano has a ~2nm TiN layer in the NMOS, whereas Intel uses ~2nm layer plus a 1nm Ta-based cap and another ~4nm TiN on top of that in their PMOS. Fig. 6 indicates that this extra material could be enough to move the work function in Intel's transistor from NMOS to PMOS.
Fig. 6 Effective Work Function of TiN electrode when 10-nm thick ALD TiN and TaN Films are Used as Overlayers on ~3.6 nm TiN Layer 
Fig. 7 Experimental GLOBALFOUNDRIES Transistors 
1. H.R. Harris et al., Band-Engineered Low PMOS VT with High-K-Metal Gates Featured in a Dual Channel CMOS Integration Scheme, Symp. VLSI Technology 2007, pp 154-155
2. K Choi et al., Growth Mechanism of ALD-TiN and the Thickness Dependence of Work Function, Symp. VLSI Technology 2005, pp 103-104
3. K. Choi et al., The Effect of Metal Thickness, Overlayer and High-k Surface Treatment on the Effective Work Function of Metal Electrode, ESSDERC 2005, pp 101-104
4. S. Krishnan et al., Advanced SOI CMOS Transistor Technologies for High-Performance Microprocessor Applications, CICC 2009