Archive for 2012

    IFTLE 120: SEMICON Taiwan 2012, part 1

    October 28, 2012 12:23 PM by Garrou

    This year's 3DIC forum at SEMICON Taiwan was entitled “3D-IC Supply Chain Readiness.” With most industry leaders who are currently involved in 3D development believing that the realization of 3D-IC technology into high-volume manufacturing is not a question of “if” but rather only a question of “when,” this year's forum was focused on industrial readiness and infrastructure maturity. Representatives from manufacturing supply chains, ranging from EDA to foundry/OSAT, shared their views through presentations and an open panel.




    Dr. Ho Ming Tong (left) , general manager and chief R&D officer of ASE and Dr Mike Ma, VP of Corporate R&D for Siliconware, chaired the Symposium and delivered opening remarks. Speakers included Amkor, Aptina, Cadence, EVG, LSI, Teradyne, Tohoku-MicroTec, UMC, and Xilinx

    UMC

    Kurt Huang gave a presentation entitled “Foundry TSV Enablement For 2.5D/3D Chip Stacking” -- making it clear that they will be ready to compete with TSMC in the foundry interposer and 3D stacking business.

    Recall UMC has been looking at the 3DIC area for quite a while, having been in a developmental relationship with Elpida and PTI [see IFTLE 8, “3DInfrastructure, Announcements and Rumors”] since 2010.

    UMC envisions several work flow models (shown below) and concludes that each OSAT / foundry will have their own capabilities and preferences.




    UMC indicates that their foundry design rules for interposer fabrication are ready to go, with product level packaging & testing and reliability assessment scheduled for completion in 4Q 2012.




    Typical 3D TSVs are 6 x 50 and for interposer are 10 x 100μm. KOZ have been determined to be 5μm for 28nm HKMG core device with TSV pitch: JESD229 50/40μm.

    Amkor

    Min Yoo of Amkor Taiwan gave a presentation entitled “3D IC Technology: The OSAT Perspective.” Amkor sees: (1) partitioning logic blocks into higher-yielding sub-blocks as is being done by Xilinx and others in the FPGA arena -- this results in lower cost 28nm products as well as chips that are less sensitive to 28nm processing issues; and (2) repartitioning SoC devices into separate functions which allows for using the latest node (i.e. 28nm) only where it is required. The latter has been discussed previously by Bryan Black of AMD [see IFTLE 80, [email protected]].




    Also of interest is the Amkor roadmap showing Application processors + DDR for smartphones and tablets being scheduled for 2014.




    Amkor, as expected, is in favor of a supply chain where the TSV are fabricated by the fab / foundry and then shipped to the OSAT for subsequent processing.

    They highlight the fact that they are involved with the current Xilinx FPGA product . Their copper pillar μbump technology is commercial at 40μm, demonstrated at 30μm, and in development at 20μm.




    We will continue with more presentations from SEMICON Taiwan next week.

    For all the latest in 3DIC and advanced packaging stay linked to IFTLE..........................................

    IFTLE 119 ICECool Puts 3D Thermal Issues back in Focus

    October 21, 2012 4:21 PM by Garrou
    Keeping it Cool

    Back in 2008 we addressed 3D cooling activities [see PFTLE 43, "Keeping it cool in the dog days of summer"] looking a the activities at IBM Zurich, GaTech, and CALCE (U Md) as the groups especially active in this area.

    Since then we have looked further at the liquid cooling activities of Bakir at GaTech [see IFTLE 83, "Orange County IEEE CPMT 3DIC Workshop"] and Brunschwiler at IBM Zurich [see "IBM to use water cooling for future 3D IC processors"] and the fact that one of the drivers for 2.5D is that it offers better thermal performance that current 3D stack solutions [ see IFTLE 97, "DATE in Dresden, Synopsys 3D EDA solution"]. For the most part, though, IFTLE has taken the position that thermal would not be the roadblock for 3DIC and that initial products would be ones where the thermal solution was not driving the technology.

    Now that we are quickly approaching full commercial production of a number of products, it's probably a good time to focus more on proposed thermal solutions for the future. To update yourself on where things stand, I suggest Herman Oprins' article "Modeling and experimental characterization of hot spot dissipation in 3D stacks." He concludes that thermal management issues in these 3D stacks are one of the main challenges for 3D integration since the use of polymer adhesives with low thermal conductivity, the presence of interconnection structures, back end of line (BEOL), redistribution layers (RDL), and through-Si vias (TSVs) increases the complexity of the conductive heat transfer paths in a 3D stack.

    Oprins concludes that hot spot power dissipation results in significantly higher temperatures in 3D stacked chips compared to the same power dissipation in single 2D chips. This temperature increase is mainly due to the reduced thermal spreading in the thinned dies on the one hand, and to the use of adhesives with low thermal conductivity for the vertical integration of the chips on the other hand. To limit the temperature increase in 3D-ICs, "too thin chips should be avoided" because the thinner the silicon substrate, the higher the thermal spreading resistance is in the case of hot spots. Simulations show that a minimum die thickness of 50μm is required to deal with the local hot spots on the thermal test chip they used.

    Their study on the impact of TSVs on the temperature profile in the test chips showed that the presence of the die-die connections, such as Cu or CuSn microbumps or direct Cu-Cu bonds, is more important than the presence of the TSVs itself. The Cu TSVs with high thermal conductivity (390 W/mK) are inserted in the Si, which is conductive (150 W/mK at room temperature and120 W/mK at the operating temperature). Conductivity values for the underfill materials are typically 0.2 W/mK for unfilled underfills and 0.3-0.4 W/mK for filled underfills, depending on the amount and type of filler particles. The difference in thermal conductivity between the metallic bonds and the adhesive material is thus two orders of magnitude. As a result, "well placed dummy microbumps, rather than dummy TSVs, can be used to increase the effective thermal conductivity and to reduce the temperature increase in a 3D stack."

    Many of you are aware of DARPA's BAA 12-50 ICECool an effort of CALCE's Avi Bar-Cohen within DARPA's Microsystems Technology Office (MTO). ICECool Fundamentals is the initial thrust and first BAA of DARPA's ICECool program.

    The specific goal of ICECool Fundamentals is to demonstrate chip-level heat removal in excess of 1 kW/cm2 heat flux and 1 kW/cm3 heat density with thermal control of local sub mm hot spots with heat flux exceeding 5 kW/cm2, while maintaining these components in their usually accepted temperature range by judicious combination of intra- and/or interchip microfluidic cooling and on-chip thermal interconnects. ICECool Fundamentals is, thus, the first step toward achieving the system performance goals of the ICECool program and will develop the fundamental building blocks of intrachip and interchip evaporative microfluidic cooling.

    ICECool Fundamentals will, over an anticipated 24–36 months, develop and demonstrate the microfabrication techniques needed to implement thermal interconnects and evaporative microfluidics in multiply-microchanneled semiconductor chips, and study, model, and correlate intrachip heat diffusion and the thermofluidic characteristics of evaporative flows in microchannel flow loops within individual chips and/or in the microgaps between chips in 3D stacks -- without compromising the combination of intra- and/or interchip microfluidic cooling and on-chip thermal interconnects in one of several possible semiconductor wafers.

    They offer the following schematic as an interchip approach:




    and required responses to deliver on the following metrics.




    There will be several winners to this first "fundamentals" BAA and hopefully we will be seeing the next generation 3DIC thermal stacking technology evolve from the government-supported program. IFTLE will keep you informed as the winners are announced and their proposed thermal solutions become public.

    For all the latest on 3DIC and advanced packaging stay linked to IFTLE......................................

    IFTLE 118 IMAPS 2012 part 2

    October 13, 2012 9:50 AM by Garrou
    Continuing our look at 3D and advanced packaging presentations at IMAPS 2012.

    Shinko and CEA Leti

    With the recent announcements by Xilinx, Altera and others the commercial production of 2.5D products on "high density" interposers is entering the realm of commercial reality. While it is clear that fine featured interpsoers will come from foundries like TSMC, there have been questions, about "coarse featured" interposers in terms of who will make them and what applications they will be used in. [see IFTLE 94, "Experts discuss interposer Infrastructure at IMAPS Device Pkging Conf"]

    Shinko and Leti now describe integration and electrical characterization of such a "coarse featured" 3D silicon Interposer demonstrator for a SiP application. This demonstrator consists of (4) 10 × 10 mm chips mounted on a 26 × 26 mm Si interposer with 25µm microbumps on 50µm pitch and underfilled. TSV diameter are 10µm and interposer thickness is 100µm for an Aspect Ratio (AR) of 10. We are told that RDL on both sides of the interposer are done with a "semi additive process" although we are not given line width or pitch. We assume these are "coarse pitch" meaning 5µm or greater.

    The populated interposer is then mounted on the PWB using Sn-57Bi solder to achieve low temp reflow. These packaged test structures were tested for TSV continuity and via chain resistance. These packages also survived 100 hrs at 125°C, 1000 cycles from -55 to 125°C, and 1000 hrs of HAST.




    IBM Japan

    IBM Japan reported on the warpage and mechanical stresses generated during chip and interposer assembly processes. Chip and package assumptions are shown below.




    They modeled the following sequences:




    Sequences are each divided into two steps, with either chip joining or interposer joining being the first step.

    In the chips first sequence, interposer warpage is caused by CTE mismatch between interposer and RDL. Results are highly dependent on the thickness of the interposer. A 100µm to 200µm thick interposer can have more than 200µm displacement which will make it difficult to mount to the organic substrate. Underfill between the chips and interposer inhibits warpage.

    Warpage of the interposer in the interposer to laminate first sequence is convex. A 100µm glass interposer shows less displacement than silicon.

    The evaluated Von Mises stress on the interposer to substrate solder balls and found the largest stress was developed by the thickest silicon interposer and the lowest on the thinnest glass interposer.

    IMEC

    In their paper "Stacking Aspects in the View of Scaling", IMEC points out that when pitch goes below 40µm "stacking accuracy is one of the main drivers to ensure yielding devices." It is shown that stacking can be made less sensitive to in plane misalignment by the obvious options of increasing the pad size or decreasing the solder bump size, i.e. making the landing pads on the interposer larger than the bumps on the chip makes up for misalignment.

    In a second presentation, "Small pitch microbumping and experimental investigation for underfilling 3D stacks," they report on 3D stacking characterization when using pre applied underfill.

    For 3D stacking capillary underfilling has clear limits in terms of the gap between die and the bump pitch. This limits high density integration and therefore shifts focus onto pre applied underfill where the material is dispensed on the landing die before stacking. Pre-applied UF does have concerns such as transparency for alignment marks and UF/filler entrapment between bumps.

    IMECs studies reveal that both NUF/NCP (define) and WUF (wafer underfill) have commercial products that result in >90% electrical yield after underfilling, although issues such as delamination of WUF films was observed.

    Thin chip stacking using B2F technology

    For many years PFTLE and IFTLE have been proponents of die thinning for 3D IC stacks because it not only has an effect on the final thickness of the product, but also has a direct effect on the TSV AR. When die are thinned to i.e. 25µm they can be stacked B2F without TSV and metallized over the edge to make interconnect. This technology was first described by Toepper from Fraunhoffer IZM.

    In this presentation, ST Micro, CEA Leti, Datacon, Disco, and EVG presented two approaches have been investigated for B2F bonding of the thinned die: (1) applying a die attach film (DAF) bonding layer, or (2) using spin coated polymers for the die attach.

    Thin die prep is required. In order to obtain good step coverage, die are singulated at 45° to provide edge slope. Once mounted on tape, plasma stress relief is applied. Without plasma treatment of the backside and edges, they found 100% of the die broke during the subsequent pick and place operation.

    Using DAF is an acceptable solution but placement accuracy was degraded due to the presence of the DAF under the die and tool clogging by the DAF.

    Spin-on polymer was found to be a better solution. They examined BCB, PI, and AL-X . PI showed outgassing and AL-X was not tacky enough so they down selected BCB.

    For a capping insulation layer they examined: (1) conformal encapsulation by CVD low temp oxide; (2) thin conformal encapsulation by spin or spray coated polymeric films; and (3) thicker planarizing encapsulation using spin on polymers. The best solutions were found to be: (a) 200-240 C LTO in combination with the BCB adhesive layer, or (b) spray coating of positive, photo WPR 5100 from JSR. JSR thick resist THB151N was used to make contact from the top to the bottom chip.

    For all the latest on 3DIC and advanced packaging stay linked to IFTLE....................

    IFTLE 117: Tezzaron acquires SVTC fab; 3DIC activity at IMAPS 2012 part 1

    October 7, 2012 12:00 PM by Garrou
    Tezzaron acquires Texas SVTC facility

    Bob Patti of Tezzaron Semiconductor has been touting the merits of 3DIC for longer than most everyone else in our industry. Bob first announced a partnership with Chartered Semi to scale up his memory through-silicon via (TSV) technology back in 2007 [see PFTLE13: "50$ bonding and Intel announces 'We are ready'"].

    Tezzaron has always been at the leading edge, offering 2µm pitch W TSV several years ago. Being ahead of the industry, frankly, they have had issues working through the regular supply chain.

    Last week Tezzaron took a major step toward alleviating that problem with the announcement that it is acquiring the wafer fabrication facility of SVTC Technologies in Austin, Texas. You old-timers will recall this as the SEMATECH fab in Austin. Tezzaron will continue the operation of this facility while adding capabilities to assemble its own 3DIC devices. Tezzaron indicates that they will be operating the fab with the same employees in the same location.

    IMAPS 2012

    The 45th Symposium on Microelectronics (IMAPS 2012) was held a few weeks ago in San Diego. Let's look at some of the 3D and advanced packaging papers presented at this meeting.

    Qualcomm

    When last we discussed Qualcomm it was complaining about constrained supply of 28nm [ see IFTLE 114, "...28nm; nickels and a symbiotic relationship"] but do we have any clarity on exactly what it is trying to build? Maybe now we do.

    Gu and co-workers at Qualcomm reported on a memory on logic 3DIC stack consisting of a two-chip-wide IO memory stack bonded to a 28nm logic chip.



    TSV are 6µm, wafers are thinned to 50µm, TSV connection is to M1 of the 7-layer copper/low-k interconnect stack. The memory stack has 1200 IO on 40µm pitch. The bottom memory die has TSV, the top die does not need them. Thinned die are shipped either on their carrier (OSAT removes the carrier) or after removal from the carrier on a flex frame.

    Negligible shift in electrical parameters are observed after optimizing TSV formation and determining the need for a 5µm keep-out zone (KOZ). No change in bump resistance is seen after 1000 hrs at 150°C and 1000 cycles of temp cycling. Memory function was verified after full assembly of the stack.

    Xilinx

    Xilinx has been releasing information on its 2.5D FPGA module for the past two years. [See IFTLE 73, "Xilinx shows 2.5D Virtex 7 at IMAPS 2011" and IFTLE 23, "Xilinx 28nm multi-die FPGA, copper pillar advances at Amkor, and Intel looking at foundry options."]

    In this latest presentation, Banijamail and co-workers examine the reliability of their 2.5D Virtex-7 H580T which consists of a transceiver chip and two FPGA slices. Interposer TSV are 10-20µm and 50-100µm deep. FPGA chips are bumped on 30-60µm pitch using Cu pillar bump technology.

    Different substrate sizes and designs, lid designs, lid materials, and underfills were examined to minimize warpage and maximize microbump and c4 bump reliability. Control of these variables resulted in packages that met JEDEC warpage spec and minimized BGA fatigue.

    Applied Materials

    IFTLE has detailed many times how Applied Materials is making 3DIC a focus area for its equipment business. [see IFTLE 95, "Time flies when you're having fun: Further details on the Micron HMC, equipment suppliers continue consolidation, EVG temp adhesive open platform" and PFTLE 72, "Samsung 3-D 'roadmap' that isn't."]

    Eaton and co-workers from Applied Materials now present process detail on how scallop-free TSV can be etched in their Silva etch chamber. Complete scallop removal added ~10-15% to the time to etch a 10 × 100 TSV with 30nm sidewall scallops.

    SEMATECH

    SEMATECH reported on their examination of the copper protrusion issue. While they quote a few past references such as my friends Paul Ho and Jay Im at UT Austin, to give credit where credit is due, they leave out what I think are the key references to the area [see "Researchers strive for copper TSV reliability," Semiconductor International, Dec. 3rd 2009], which include Bob Patti at Tezzaron whose cross-sections first brought the protrusion question to the public eye; Paul SibelrudPaul Sibelrud (then at Semitool) who extensively studied the extent of the problem and the composition of the extrusions; and most importantly Eric Beyne at IMEC who was the first to disclose the thermal anneal solution for the problem.

    For those of you new to the area, after TSV are filled with copper and planarized by CMP they are subsequently exposed to >350°C downstream processing during which time Cu, due to a higher CTE, expands more that the surrounding silicon and extrudes out beyond the planarization point and stays there upon cooling due to its plastic deformation properties. This expansion also causes stresses to be generated which in turn require a KOZ (keep-out zone) to be defined so said stresses do not negatively impact the transistor electrical performance.

    The goal of this SEMATECH study was to look for "possible mechanisms that cause copper protrusions by varying process conditions." The TSVs studied were 5 × 50 lined with 500nm of TEOS oxide and Ta/TaN diffusion barrier, which were then annealed at 150°C for an hour and CMP'ed. Samples post CMP were annealed at seven different temperatures .

    The researchers outline a number of methods of detecting the protrusions and give +/- for them. They chose optical imaging and AFM as their methods of choice and micro raman spectroscopy to determine post-CMP anneal stress.

    As expected, stress increases as the post anneal temp increases and copper protrusions range from 50nm to 400nm when annealed (post plating) from 150°C to 400°C. In agreement with the previous studies by Sibelrud, they find that plating bath chemistry has a major impact on protrusion. They link this to whether the copper is in a tensile or compressive state. They suggest that copper grown in a tensile stress state is a significant contribution to protrusions after thermal annealing at high temperature.

    Next week we will finish our look at IMAPS 2012.

    For all the latest in 3DIC and advanced packaging stay linked to IFTLE...............................

    IFTLE 116: A6 applications processor for iPhone 5 from Samsung, but...

    September 25, 2012 12:27 PM by Garrou
    Many of you may be wondering why IFTLE has recently been paying so much attention to the Apple A6 processor. Well, TechInsights reports that in the last 5 years Apple has generated over $150 billion in revenue from the iPhone family of handsets and accessories, and over 100 million units of the iPhone have been purchased by consumers [link].

    We have mentioned before that the A6 is the odds-on favorite to be a major driver for bringing 3DIC (or at least 2.5DIC into high volume manufacturing). A few weeks ago we reported that TSMC felt confident about securing Apple's foundry business for the A6 and A7 processors based on its 28nm and 22nm processes [see IFTLE 112, "TSMC staffing up for 2.5/3D expansion"]

    Last week we informed you that the Taiwan Economic News had reported that pilot production of Apple processors was expected to start in the first half of 2013 with volume production following in the second half." [link]

    Since the introduction of the iPhone in 2007, there have been five generations of iPhone models, each one improving on the technology used for the preceding model.





    Comparison of Apple application processors [Chipworks]

    Apple has partnered with Samsung for every generation of their application processors but recent Apple-Samsung lawsuits over patents related to competing handsets has lent credence to the rumors that Apple was going to switch production to TSMC.



    What we now find is that this first generation of the A6 is still manufactured by Samsung as confirmed by both TechInsights [link] ("Our initial SEM cross-sections of the A6 processor show metal and dielectric layering that is almost identical to that used in the previous A5 processor ... Early analysis of the die markings of the A6 reveal markings that are similar to the Samsung markings found in the A4 and A5 processors") and Chipworks [link] ("What we can say is that the foundry for the chip we have analyzed is confirmed to be Samsung and that [...] this chip has a custom designed ARM core [...] and has a triple core graphics processor unit").

    Thus, multiple trusted sources agree that the A6 looks like it is being manufactured by Samsung 32nm technology.

    The A6 is also the first Apple processor to use its own ARMv7 based processor design. The CPU cores aren't based on the A9 or A15 design from ARM IP, but instead are something of Apple's own design [link].



    Apple A6 processor (Techinsights)

    Conclusions

    This information makes complete sense vs. the recent announcements indicating that TSMC was scaling up in 2013 (obviously not ready for last week's production release). IFTLE concludes that it is likely that the 2nd-gen A6 will be done in 28nm technology by TSMC similar to the 45nm and 32nm versions of the A5 (as shown in the table above), and this is the point of entry for the TSMC 2.5D technology. The timing for this appears to be 2013. What Apple product will be the point of entry? IFTLE will stay on top of this evolving technology story.

    For all the latest in 3DIC and advanced packaging, stay linked to IFTLE...........................

    IFTLE 115: No nickels; SCP quals low-volume TSV manufacturing; 3D IC slowdown; Apple/TSMC timetable

    September 11, 2012 2:18 PM by Garrou
    Don't believe everything you read!

    Well, no sooner did we upload the blog last week [see IFTLE 114, "28nm capacity, nickels, and a symbiotic relationship"] than a local reader brought to my attention that the "Samsung pays off Apple in nickels" story was shown to be a hoax [link]. Even though my link was to Google-Nexus, not some crazy blogger with no credibility, I should have known better. I guess part of me simply wanted it to be true .... what a great move it would have been! Kind of like Clint Eastwood telling off the President of the United States. I asked the question, how and where do you get 20B in nickels? [Much less the logistical trouble of transporting 20B nickels weighing in excess of 100,000 tons.] So I should have followed my gut, or at least ran this by my BS meter! I guess I'm not any smarter than those who have spent the last 4 years "hoping for change" (pun intended) but never got it.

    So I guess the only lesson we learned here is: Don't believe everything you read.

    STATS ChipPAC quals 300mm low-volume TSV manufacturing capability

    STATS ChipPAC (SCP) has announced that its "TSV capabilities have achieved a new milestone with the qualification of its 300mm mid-end manufacturing operation and transition to low-volume manufacturing." [link] Reportedly SCP is engaged with multiple strategic customers on TSV development programs for the mobile, wireless connectivity, and networking market segments. Qualification activities include devices at the 28nm silicon node, application processors (AP), and graphic processors utilizing TSV for the high-performance wide-input/output (Wide I/O) memory interface required by higher-bandwidth applications for the mobile market.

    The Company's BEOL services include chip-to-chip and chip-to-wafer assembly with stealth dicing and fine pitch micro-bump bonding down to 40μm. Dr. BJ Han, executive vice president and chief technology officer, indicates that their "primary focus has been to develop high-volume TSV technology capabilities that we can offer to customers at cost points that make TSV a viable solution. We now have mid-end manufacturing capacity in place in Singapore and are actively engaged with multiple strategic customers on the production qualification of 2.5D and 3D packaging designs."

    "3D IC commercialization to take place in 2015-16"

    Someone I still do have faith in is ASE's Ho Ming Tong, general manager and chief of R&D at ASE. According to Digitimes (Sept 6th 2012) he is being quoted as saying: "The adoption and commercialization of 3D TSV stacking IC technology and products will likely take place in the 2015-16 timeframe," whereas "2.5D TSV chips could be widely found in end products in 2014-15." [link]

    Tong points to the fact that "electronic design automation (EDA) tools are not yet mature enough for the industry's transition to 3D ICs from 2D ICs." When they finally do happen, Tong sees a broad array of applications including consumer electronics, mobile communications, PC, and automotive. The emergence of cloud computing is also expected to help accelerate the adoption of 2.5D and 3D TSV chips, he believes.

    More on TSMC and Apple

    In another story update, a few weeks ago we reported that TSMC felt confident about securing Apple's foundry business for the A6 and A7 processors based on their 28nm and 22nm processes [see IFTLE 112, "TSMC staffing up for 2.5/3D expansion."] Well, the Taiwan Economic News now reports that "pilot production of Apple processors is expected to start in the first half of 2013 with volume production following in the second half." [link]

    For all the latest on 3DIC and advanced packaging stay linked to IFTLE........................

    IFTLE 114: 28nm capacity nickels, and a "symbiotic relationship"

    September 4, 2012 12:27 PM by Garrou
    28nm yield reported to be up at TSMC

    While Nvidia is the only customer to complain about poor 28nm yields at TSMC [link], other customers like Qualcomm and Altera have reported that "constrained supplies of 28nm" has affected their sales figures. Circulating rumors suggest that Qualcomm has looked for 28nm capacity at UMC and GF but has returned to TSMC since things were even worse at its competitors.

    TSMC has announced a goal of getting its 28nm supply and demand into balance by the end of this year. According to the Taiwan Economic News, TSMC's 28nm capacity is now running at 100,000 wafers a month, up from the 25,000 wafers a month capacity in Q2. TSMC's fab 15 in the Central Taiwan Science Park is said to be ending Q3 with 69,000 28nm wafer per month capacity and will expand that to 135,000 wpm in Q4.

    While there were widespread reports earlier in the year of severe 28nm yield issues at TSMC [link] according to Taiwan's Commercial Times, equipment suppliers are reporting that TSMC's 28nm yield is now over 80%.

    But capacity shortage appears real and may constrain smartphone launches.......

    There appears to be some concern that a shortage of available 28nm chip supply might constrain the new smartphone / mobile device launches this fall. Samsung and Sony lifted the wraps on new smartphones on Wednesday; Nokia, Motorola and Amazon.com are expected to do the same next week; and all leads up to the much-anticipated announcement of Apple's iPhone 5, which many expect to happen on Sept. 12. [link]

    At a recent investment conference, Qualcomm, maker of baseband chips and application processors (like Snapdragon) for smartphones and tablets, reported that it has had trouble meeting customer demand and is trying to ramp the supply as quickly as possible.

    Would financial partners get better access to the available capacity?

    Bloomberg reports that Apple and Qualcomm have made investment offers of more than $1B each, in order to set aside production capacity exclusively for them -- but have been rebuffed by TSMC [link]. The report said that Apple's proposal was aimed at securing an alternative supplier to Samsung for chips for its iPhones and iPads, while Qualcomm, leading supplier of application processors to the rival Android platform, needs to boost supply as shortages have impacted its earnings.

    While TSMC refused to respond to what it called "market speculation," CFO Laura Ho did say that that "Dedicating one facility to a single product or customer creates the risk of a fabrication plant becoming a burden if the product, client or technology changes....You have to be careful. Once that product migrates, what are you going to do with that dedicated fab?"

    The Bloomberg report says the smartphone chip market that is worth US$219.1 billion worldwide.

    ...And speaking of Apple and Samsung......

    At present Apple relies on Samsung for its leading-edge A5 processor -- but we all know about the high-profile legal dispute with Samsung over smartphones patents, and how Apple has been reported to be working with TSMC (Hsinchu, Taiwan) to bring up a 28nm A6 processor.

    Apple may have won the recent Samsung suit concerning smartphones, but it appears that the joke was on them! [link] Google / Nexus reports that 30 trucks arrived at Apple's headquarters in California to pay the required fine. Minutes later, Apple CEO Tim Cook received a call from Samsung indicating that over the next week they would be paying the $1 billion dollar fine in nickels. Do the math: this is 20 billion nickels.




    Lee Kun-hee, Chairman of Samsung Electronics, told the media that his company is not going to be intimidated by a group of "geeks with style" and that if they want to play dirty, they [Samsung] also know how to do it. "They can use the coins to buy refreshments at the little [vending] machine for life, or melt the coins to make computers, that's not my problem, I paid them and fulfilled the law."

    IFTLE wants to know: (1) where Samsung was able to come up with 20B nickels ?? And (2) will Apple will use the nickels to pay for the next delivery of A5 chips??


    ASE response to TSMC packaging expansion

    A few weeks ago we discussed the fact that TSMC was recruiting engineers away from ASE and SIliconware to staff their 400 man packaging & test team raising questions about whether it might eventually challenge ASE and Siliconware in the packaging arena [ see IFTLE 112, "TSMC Staffing up for 2.5/3D Expansion...."]

    The Taipei Times now reports that ASE is "brushing off concerns" of a potential rivalry with TSMC amid reports that the world's largest foundry has put together a large team to make further inroads into ASE's bread-and-butter market. They quote a senior ASE executive saying that "...the company hopes to have a symbiotic relationship with TSMC" in the future.

    The traditional definition of symbiosis is "a mutually beneficial relationship involving close physical contact between two organisms that aren't the same species," like birds eating insects of the back of a rhino.




    In this case I think I know who the rhino is -- and I think the rhino has decided to use bug spray and get the birds off his back!

    For all the latest in 3DIC and advanced packaging stay linked to IFTLE.....

    Recommended 2012 Coming Events:





    IFTLE 113 An Exclusive Interview with Mr Lester Lightbulb

    August 25, 2012 4:17 PM by Garrou
    As readers of IFTLE might imagine, the recent headline "3M Claims new LED Lightbulb designed to burn for 25 years" caught my eye. The article went on to say that the bulb, which looks like a traditional incandescent, has a 25-year lifespan (at three hours of use per day) and a $25 price tag. 3M is betting the price won't be a huge hurdle for consumers because competing LED bulbs "are priced closer to $45." They then repeated the infamous refrain: "LED light costs $1.63 per year to operate -- a quarter of the cost of a traditional bulb. So even at $25, given its longevity, it still comes out where you save money over the life of the bulb."

    The bulb uses 3M's multilayer optical film, adhesives, and heat-management technology. They indicate that their marketing has determined that "prospective buyers are likely to be environmentally conscious and more affluent -- similar to those who bought a Toyota Prius hybrid in 2006." IFTLE certainly agrees 100% with the last statement.

    IFTLE has gone into great detail to show that it is the bulb that matters, not the expected life of the LED chip. If any of the components of the bulb are not rated for a 25-year lifetime the bulb should not be rated for this period of time. I checked the IFTLE BS meter for the merit of LED lightbulb ads and sure enough they rate just short of outright fraud.



    As I shook my head in disbelief that this scam of the American public was continuing unabated, with no corrective information coming from the DOE or any other Government agency [yes that was said tongue in cheek], I got a collect call from old friend Lester Lightbulb. As you know Lester is sitting on death row in San Quentin [isn't it fitting that California is the state that incarcerated him]. As he awaits the electric chair [pun intended] Lester reached out to admonish me for calling my recently failed CFL his "cousin" [see IFTLE 109: "2012 IEEE VLSI Conference ; Lester's cousin CFLDies Prematurely"].

    While I had him on the phone I thought you, the readers of IFTLE, would appreciate a direct interview with Lester.


    IFTLE: Lester, of course we know that CFL and you are not related, we were just trying to link you, CFL and LED as part of the interior lighting family.

    Lester: I'd like to thank IFTLE and its like-minded readers for supporting me as I await eradication from the face of the earth, but that dirtbag "quicksilver" is no family member of mine. Do you see a tungsten filament? NO. So he is certainly not related to me.

    IFTLE: Quicksilver... is that his nickname?

    Lester: Yes, that's what all us incandescents call him -- quicksilver is mercury and all the CFLs contain that highly toxic element. They are the least environmentally friendly source of light that we can use, which makes it quite ironic that those who claim they are trying to save the environment are about to eradicate me and use him. I guess you haven't seen the latest headlines from Sweden have you?

    IFTLE: No, please share them with us, Lester.

    Lester: "CFLs creating 'acute crisis' in Sweden." In a series of articles the Swedish newspaper Svenska Dagbladet has reported on the large scale ongoing dumping of fluorescent bulbs (CFLs), and the dangers of released mercury that goes with it [link].

    Mina Gillberg, former advisor to EU environment commisioner Margot Wallström is now regretting the consequences of their decision to switch to CFLs. "The motive for replacing incandescent bulbs with CFLs was to save electricity and thereby save the environment," but Gillberg now condemns the drive for CFLs as "absurd."

    Sweden estimates that 200,000 CFLs are thrown into glass recycling bins per year. "'This is a health risk for those who work with recycling and a risk that the environmental toxin spreads in the natural environment"..." Especially when the recycling bins are indoors, since mercury vaporizes at room temperature and contaminates the surrounding area."

    IFTLE: So mercury or quicksilver is really that big a problem, Lester?

    Lester: Mercury has long been recognized worldwide as a health hazard because its accumulation in the body can damage the nervous system, lungs, and kidneys, posing a particular threat to babies in the womb and young children. No one I have ever heard of, of any political persuasion, defends mercury.

    The British government instructs households that "...if a compact fluorescent lightbulb is broken in the home, the room should be cleared for 15 minutes because of the danger of inhaling mercury vapour." Similar warnings are on US packaging where, as we have already discussed, the consumer is directed to contact the EPA for proper disposal procedures.

    In 2009, timesonline [UK] reported extensively on the production of CFL in China, where "a heavy environmental price is being paid for the production of 'green' lightbulbs."

    Tests on hundreds of Chinese employees found dangerously high levels of mercury in their bodies and many have required hospital treatment, according to local health officials in the cities of Foshan and Guangzhou. At the Nanhai Feiyang lighting factory in Foshan tests found 68 out of 72 workers were so badly poisoned they required hospitalization. In Jinzhou, 121 out of 123 employees had excessive mercury levels."

    In 2008 Maine banned the disposal of CFL bulbs. In their tests CFLs were broken in a small/ moderate sized room and mercury concentrations in the room were continuously monitored. "Mercury concentration in the room air often exceeded the Maine Ambient Air Guideline of 300 ng/m3 for some period of time, with short excursions over 25,000 ng/m3, sometimes over 50,000 ng/m3, and possibly over 100,000 ng/m3 from the breakage of a single compact fluorescent lamp.... All types of flooring surfaces tested can retain mercury sources even when visibly clean..... Residual mercury in the carpeting has particular significance for children rolling around on a floor, babies crawling, or non mobile infants placed on the floor.... Vacuuming up the smaller debris particles in an un-vented room can elevate mercury concentrations over the MAAG in the room and it can linger at these levels for hours. And the vacuum can become contaminated by mercury such that it cannot be easily decontaminated." They indicated that the homeowner would have a decision on whether or not to "replace the carpet in the area where the bulb was broken."

    Is anyone who is buying a previously owned home thinking about whether the carpet has been contaminated with mercury? And what that means to their small children?

    So IFTLE, can you tell me why the world's governments and the world's self-described "environmentalists" are trying to eradicate the incandescant bulb and replace them with CFLs?

    IFTLE: Lester, I think it's all tied to the EPA. In 1990, EPA was given authority to control mercury and other hazardous air pollutants from major sources of emissions to the air. For fossil fuel-fired power plants, the amendments required EPA to conduct a study of hazardous air pollutant emissions. In 1999, EPA estimated that approximately 75 tons of mercury were found in the coal delivered to power plants each year and about two-thirds of this mercury was emitted to the air annually. In 2000, the EPA found that regulation of hazardous air pollutants, including mercury, from coal and oil-fired power plants was appropriate and necessary. Lester, don't you think that this is a good thing? You can't be for supporting mercury pouring into the atmosphere from our electric utilities, can you?

    Lester: No, none of us are, but the electric utilities are taking steps to reduce mercury emissions from power plants as part of ongoing pollution prevention programs. In fact, existing control technologies for sulfur dioxide (SO2), nitrogen oxides (NOx), and particulate matter have reduced power plant mercury emissions by roughly 40 percent already. All of those nasty materials need to be scrubbed as does mercury, but notice I do not include CO2...and don't get me started on that, because CO2 has gotten a worse bum rap than I have by the same ignorant environmentalists and corrupt scientists.

    IFTLE: SOX, NOX and particuate reductions are all good things, Lester. I'm with you on the C02 emissions too, Lester. CO2 rates a 5+ on my BS meter, but we shall discuss that scientific fraud another day.

    Lester: Anyway, my point is that instead of justifying toxic quicksilver light bulbs by pointing a finger at how toxic power generation is, why not continue to use safe, non-toxic, incandescent light bulbs and work on cleaning up the effluent from our power plants?

    IFTLE: Once again you make sense, Lester. Let's take a few minutes to discuss one of my pet peeves: CFL longevity. It's claimed that a CFL will last ten times longer than an incandescent [It says so right on the packaging]. When my CFL bulb recently burned out faster than my incandescent bulbs [see IFTLE 109, "2012 IEEE VLSI Conference; Lester's cousin CFL Dies Prematurely"], several readers reported that they too had experienced less than 1 year lifetime from their CFL bulbs. Hmmmm...

    Lester: The basic problem is that quicksilver bulb lifetime is impacted by how often the bulbs are turned on and off and their use temperature. Optimal use for a fluorescent light is to be left on all the time at temperatures between 50-80°F. Wikipedia indicates that "In the case of a 5-minute on/off cycle the lifespan of a CFL can be reduced to close to that of incandescent light bulbs" -- which is exactly the result that you got!

    Since a lot of light use in the home is less than five minutes (i.e., a trip to the bathroom; looking in a closet; quick night time trip to the kitchen; get tool out of the garage, etc.), a much more accurate statement for CFL packaging would be: "Lifetime is estimated at 250-10,000 hours depending on use."

    The picture below is of a CFL that failed after 200 hours [link]. The electrolytic capacitor is bulging at the end, and it had ruptured its safety seal and leaked electrolyte; the heatshrink tubing around the inductor got so hot that it split; and the capacitors are all seriously discolored.



    The only way to get the maximum life from any CFL is to keep the electronics as cool as possible -- preferably well under the manufacturers' recommendation of 50°F.

    Homeowners will also be faced with the expensive requirement to replace all non-ventilated light fittings with new ones that have sufficient airflow to maintain a safe temperature for CFL use. Because such fittings must be installed by a licensed electrician (in most countries), this is another expense that is usually ignored.

    Any potential saving in energy bills is gone ... for quite a few years, until the cost of the fittings and their installation is amortized. There is also the enormous waste of replacing perfectly good light fixtures with new ones, so the environmental impact is also negative -- probably by a large margin.

    By the way, IFTLE, I saw that you threw your CFL bulb away with the garbage. Hope you won't be doing that anymore after our little discussion on mercury!

    IFTLE: Wow, Lester, that's a lot to think about. Anything else you want to share with our readers?

    Lester: Yes, I'd like them to read the 2009 NY Times "green blog" interview with Howard Brandston. He is the award-winning lighting designer who helped develop the nation's first standards for energy-efficient building design.

    Mr. Brandston accuses "energy zealots" of using "faulty science" to determine the efficiency of light bulbs. To quote Mr Branston: "The calculations used by the government and others promulgating or promoting use of CFLs is strictly mathematical conjecture and has nothing to do with reality."

    When asked whether we shouldn't be doing all we can to cut down the amount of power usage, he responded: "But hoping that lighting is going to make a major contribution [to the reduction of power usage] borders on ridiculous. The real areas that should be looked at that would make big gains are in all commercial office buildings. If they raised the temperature in the summer that they would cool to and lowered the temperature that they would heat to [...] we would save more energy in a few months than all the lighting watts per square foot baloney that's going on now."

    Basically, IFTLE, his conclusions are the same as yours when you looked at how much lighting contributed to the overall power usage in your house: "If you're trying to save energy, that isn't the place to start." [see IFTLE 98: Lester the Lightbulb vs. CFL and LED: The saga continues]

    IFTLE: Lester, as always it has been a pleasure. I sincerely hope we can turn things around and get you a pardon, for your good and the good of the country.



    For all the latest on 3DIC, advanced packaging and the exploits of Lester the Lightbulb stay linked to IFTLE..............................

    IFTLE 112 TSMC Staffing up for 2.5/3D Expansion ; Semi 3D Standards; Sony shows off 3D stacked Image Sensors

    August 20, 2012 9:04 AM by Garrou

    The Latest from TSMC

    Ken Liu of Taiwan Economic News reports that TSMC is aggressively hiring for their 2.5/3D packaging and test unit and will have a team of over 400 specialists ready for this business area [link]. Reports are that they have hired experts away from ASE, Siliconware and Powertech to fill these vacancies.

    In the past IFTLE  has insinuated that TSMC was working with a half dozen primary customers in the 2.5D area. Liu now names them as Xilinx, AMD, Nvidia, Qualcomm, TI, Marvell and Altera Corp.

    Reports in Taiwan are that TSMC lost the chance for making Apple A3 processors to Samsung because of its lack of the capability to package and test the chips. TSMC management reportedly now feels confident of securing Apple's foundry contracts for next-generation processors. The A6 ??
    Per Steve Liebson here is a close up of the TSMC / Alterra  2.5D (which TSMC is now calling their chip-on-wafer-on-substrate CoWoS technology) test vehicle which we have previously described [ link]. It was evidently was on display at the Cadence booth at the recent design automation conference. TSMC describes the 2.5D circuit  as being composed of 65 nm GPS, 45 nm DRAM and 28 nm SoC.

    (Click on any of the images below to enlarge them.)


    
    3DIC SEMI Standards

    The Inspection and Metrology Task Force  of  the Semi 3D standards group, recently approved its first Standard ,SEMI 3D1, Terminology for Through Silicon Via Geometrical Metrology. SEMI 3D1 will provide a starting point for standardization of geometrical metrology for selected dimensions of through silicon vias (TSVs). Although different technologies can measure various geometrical parameters of an individual TSV, or of an array of TSVs, such as pitch, top diameter, top area, depth, taper (or sidewall angle), bottom area, and bottom diameter, it is currently difficult to compare results from the various measurement technologies as parameters are often described by similar names, but actually represent different aspects of the TSV geometry.

    Other standards under development by the  Inspection & Metrology Task Force include SEMI Draft Document 5270, Guide for Measuring Voids in Bonded Wafer Stacks, SEMI Draft Document 5409, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks, SEMI Draft Document 5410, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures, and SEMI Draft Document 5447, Terminology for Measured Geometrical Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures.

    The Thin Wafer Handling Task Force is focused defining thin wafer handling requirements including physical interfaces used in 3D-IC manufacturing. Current standards for shipping are not well-suited for the reliable storage and transportation of thin wafers and dice on tape frames used in 3D-IC manufacturing. Wafer thicknesses of 30-200um will need significant changes to the current design criteria of current wafer transport and storage containers. SEMI Draft Document 5175 aims to address the robust handling and shipping of thin wafers, including changes in securing the wafers.

    The Bonded Wafer Stacks Task Force is near completion of its SEMI Draft Document 5173, Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack and SEMI Draft Document 5174, Specification for Identification and Marking for Bonded Wafer Stacks.

    Current wafer standards do not adequately address the needs of wafers used in three-dimensional bonded wafer stacks for stacked integrated circuits. In each step of a 3D-IC process, the incoming material must be specified in terms of wafer dimension and materials present. Wafer thickness, edge bevel, notch, mass, bow/warp and diameters change when wafer stacks are bonded, debonded, and when wafers incorporated into stacks are thinned. Further, these parameters will change for a single wafer stack during process. This Document will provide the required properties of both silicon ("device") wafers and glass ("carrier") wafers to be used in 3D-IC applications. Templates for describing bonded wafer stacks and processed wafers to be used in the bonding flow would be provided as well.

    The Middle-End Task Force is focused on the middle-end processes on wafers with or without TSVs, including post-final metal temporary bonding, wafer thinning, TSV formation and reveal, micro-bumping, redistributed line formation and carrier de-bond. The task force's first two proposals are SEMI Draft Document 5473, Guide for Alignment Mark for 3DS-IC Process, and SEMI Draft Document 5474, Guide for CMP and Micro-bump Processes for Frontside TSV Integration.

    Further details on the Semi standard efforts can be found here [link]. 

    Sony Stacked Image Sensor

    CMOS image sensors are used in a wide range of Sony products, including digital cameras, digital camcorders, DSLR cameras and Android based smartphones. Sony has focused on key traditional parameters such as increased pixel counts, improved resolution and higher speed. January 2012, Sony announced that it had successfully developed a 3D stacked CMOS image sensor complete with TSV. In place of the supporting substrate used in conventional back-illuminated CMOS image sensors, this image sensor stacks  the back-illuminated pixels layer onto chips containing the circuit section for signal processing which facilitates greater functionality and compactness. The new structure is positioned to become the next generation of back-illuminated CMOS image sensors.

     In the figure below Sony compares their new stacker CMOS image sensor to previous advancements such as Exmor (on chip column parallel A/D conversion) and Exmor R (backside illuminated). The size gains are obvious.
    For all the latest in 3DIC and advanced packaging stay linked to IFTLE...........................

    IFTLE 111 New Temporary Bonding Technologies Introduced at Suss 3D Workshop

    August 12, 2012 9:15 AM by Garrou

    At the recent Semicon West, Suss, which supports all commercially available temporary bonding solutions, held their annual 3D workshop.

    (Click on any of the images below to enlarge them.)


    IMEC
    Eric Beyne of IMEC reported on 3D technology status. He sees:

    - a clear industry convergence on Cu-TSV, vias middle with TSV dimensions 5 x 50 um. 
    - a significant challenge is still a  wafer carrier system for wafer thinning with high precision and compatible with further backside processing
    - as the technology matures they see a stronger emphasis on fine pitch die-to-die stacking : 40 µm Þ 20 µm Þ 10 µm
    Beyne sees current application focus areas as:
    

    When looking at all the studies performed on TSVs the literature offers the following conclusions:
    


    IMEC is moving their standard process from 5 um in 50 um thick silicon to 3 um in 50 um thick silicon. They see this soon moving to 2 um TSV in 30 um silicon which is an AR of 15. They see the standard interposer as 10 um TSV in 100 um thick silicon.

    Ga Tech

    Venky Sundaram of GaTech updated the audience on "Glass as an Ideal Material for Interposers, Packages and System Integration." The two interposer programs at GATech are focused on Low Cost Silicon Interposers and Packages (LSIP); (a) wafer based; (b) panel based and Low Cost Glass Interposers; (a) wafer based and (b) panel based
    According to Sundaram glass has the following attributes:


    
    Although glass does have its challenges:


    They see two commercialization paths for glass. They eventually see glass wafers as 2X less cost and panel based glass as 10X based glass. 


    AMKOR
    Ron Huemoeller of Amkor looked at the migration of SoC to 2.5D. This can occur by breaking up large pieces of logic into smaller chips and mating on an interposer or breaking up a large monolithic die into functions and mounting on an interposer.


    
    

    The former is exemplified by the now infamous Xilinx FPGA interposer development which Amkor is in the process of assembly scaling up.

    Amkor sees 2.5D assembly challenges as:
              Die-Die X-Y Spacing
           -      Fillet sizes and pad metallurgy and materials
    -        Process assembly sequence ; Micro-join method
              Die-Die / Die-Substrate Joining
           -        Micro bump uniformity ; Method of Join ; Materials
              Thermal and Power Management
           -        Use of Lids, Stiffeners and Passives
           -        Underfill/Resin bleed, adhesive compatibility
           -       Process assembly sequence and materials
              Warpage Control
          -        Interposer warpage ; Substrate warpage
          -        Top die warpage - area density/distribution
              Intermediate e-Test Points
          -        Process assembly sequence

    Assembly options include chip on substrate, chip on wafer and chip on chip all of which have pros and cons.

    This was followed by the introduction to tree new temporary bonding solutions that Suss is working on with Dow Corning, Dow Chemical and 3M.
    Jim Rosson of Dow Corning introduced a bi-layer, temporary bonding solution with a  room temperature de-bond. This silicone solution consists of a WL-30XX Release layer and a  WL-40XX Adhesive layer.
    De-bonding consists automated mechanical de-bonding at room temperature on Suss de-bonders
    The wafer is solvent cleaned on flex frame with compatible solvents and the carrier wafer is cleaned by standard processes.
    Dow Corning is currently expanding their beta test program of this temporary bonding system.
    Jeff Calvert introduced Dow Chemicals new BCB based temporary bonding solution XP-BCB.
    AP-3000 adhesion promoter is spun onto the carrier wafer followed by  XP-BCB onto active die wafer.

    The temp adhesive is cured at 210-230C for 10-30 min. De bonding is done mechanically at RT due to the lower adhesion of BCB to the device wafer.

    Blake Dronen of 3M described their next generation Wafer Support System (WSS).
    Gen II WSS uses conventional WSS materials but adds a high temperature thermoplastic primer layer to the substrate surface as a surface for the UV curable adhesive to bond, independent of the wafer surface passivation material.  Upon laser degradation the LTHC layer and removal of the glass , the WSS adhesive joining layer can be peeled off the primer surface in a conventional manner.  The  thermoplastic primer is solvent rinsed, eliminating any opportunities for residue or imparting bump damage by the peel step.  This process reportedly will be ready for release in 4Q.
    An LTHC free process is also being developed to simplify glass recycle and reduce overall process cost by eliminating the debonder laser. It uses the conventional WSS materials but replaces the LTHC layer with a 100% solids UV curable "release layer" that is tuned to enable mechanical separation of the carrier at the interface.   The adhesive joining layer, when cured, becomes a single component with the release layer, peeled as one during debond. The LTHC free process is currently being developed and optimized.

    Chris Rosenthal of Suss reported on their  high throughput modular equipment platform for temporary bonding and debonding. Adhesive thickness requirements depend on the application:

    Suss has concluded that room temperature lift-off debonding is fundamentally less risky than thermal slide debonding.
    Suss introduced the XBC300 Gen2 for Room Temperature Debonding and Cleaning.
    For all the latest on 3DIC and advanced packaging stay linked to IFTLE..................................



    

    IFTLE 110 Samsung Breaks Wall of Silence at DAC 2012

    August 6, 2012 10:34 AM by Garrou

    Design Automation Conference  2012

    At the design automation conference in June Samsung, who has been on absolute lockdown when it comes to 3DIC materials leaking out of the company, opened the door...just a little bit with Samsung foundry indicating that they will be  ready to release 3D TSV Technology and Wide IO Memory Solutions "in early 2013."

    Samsung's message as to the major attributes of 3DIC vs a package on package solution (PoP) are summarized in the slide below:

    (Click on any of the images below to enlarge them.)

    In terms of wide IO memory solutions they report that they will have wide IO DRAM (Non-JEDEC type ball interface) ready for customer sample in early 2013 and will also have JEDEC standard wide IO DRAM2 .

     They claim that TSV PDK and Design Methodology has been proven for  32nm node:

    Not a lot of info, but at least an official indication that Samsung foundry is getting ready and we should be seeing products in les than a year.

    Larger Silicon Interposers are Coming

    Up to now, silicon interposers have been limited in x,y dimension to the field size of the steppers being used or 35 mm sq. It is no coincidence that the size of the Xilinx FPGA interposer is 35 mm.

    At the recent Semicon West, USHIO (link) introduced a large-field stepper lithography tool targeting interposer fabrication for 2.5D/3D semiconductor packaging applications.

    Using a 70 mm projection lens the new litho tool is capable of a  50 x 50 mm field size. They are also indicating that by 2013 they will be introducing  100 mm projection lens, which will increase the field size to 70 x 70mm.  Overlay accuracy is reportedly less than 500nm. Alignment is IR transmission based.

     EVG Wafer Bonding System first to Pass Equipment Maturity Assessment at Sematech
    EVG announced that its GEMINI Automated Wafer Bonding System has become the first product to pass a systematic, rigorous Equipment Maturity Assessment (EMA) implemented within SEMATECH's 3D Interconnect program. The Sematech assessments are designed to determine equipment readiness for high-volume manufacturing (HVM).

    The  EVG GEMINI exceeded Level 3 equipment maturity requirements -- the highest assessment rating awarded before transfer of new manufacturing processes into pilot lines or HVM.  Temporary adhesive bonding, silicon fusion bonding, and metal thermocompression bonding processes have been investigated on 300-mm wafer bonding system installed at CNSE in Albany, New York.

    SEMATECH qualified wafer bonding alignment accuracy of less than 500 nm exceeding the wafer alignment specs of the ITRS for 2018.  Sitaram Arkalgud, director of SEMATECH’s 3D Interconnect program indicated that EVG is the first company to pass ISMI's Equipment Maturity Assessment methodology.

     For all the latest in 3DIC and advanced packaging stay linked to IFTLE......................

    IFTLE 109 2012 IEEE VLSI Conference ; Lester’s cousin CFL Dies Prematurely

    July 7, 2012 7:26 PM by Garrou

    The  IEEE Symposium on VLSI Technology  is sponsored by the Electron Devices Society -- ED and the  Solid-State Circuits Society -- SSC. At this year's conference, Micron gave further details on their hybrid memory Cube and TI detailed their studies on TSV induced stress on 28nm CMOS and Chuo Univ described a hybrid NAND + ReRAM SSD stack with better power consumption and product lifetime.
    Hybrid SSD memory stack with ReRAM and TSV

    Perofessor Takeuchi of Chuo Univ described a hybrid SSD architecture using ReRAM and high capacity NAND flash memory.

    When SSDs are used for servers in financial institutions, performance is hindered and power consumption increased because random access is dominant. This causes data to get split up if the size of the data packets are not of the appropriate size (minimum for NAND is 16Kb). Takeuchi's memory stack combines a NAND flash memory and ReRAM. ReRAM is used as both cache and storage memories. To overwrite a small amount of data in the NAND flash memory, software transfers the page of data to the ReRAM so that data is not fragmented in the NAND flash memory.

    (Click on any of the images below to enlarge.)


    A prototype, tested on an emulator, showed that compared with existing SSDs which only use NAND, the hybrid memory stack achieves an 11X higher data writing performance, 93% lower power consumption and 6.9 times longer product life. This assumed that the controller, ReRAM and NAND flash memory were connected by TSV. Although this has been hyped up by several reporters, we should note that it is possible to achieve almost the same results without using TSV. The major gain of using the TSV appears to be a 14% decrease in energy required to write as shown in the comparative table below.  


    It is proposed that SSD in data centers would have to be changed out about 7 times less thus reducing expenses.

    It should be noted that in order to use  the hybrid SSD architecture for different applications, it is necessary to change the controlling software algorithms.

    Micron Hybrid Memory Cube (HMC)
    We have previously discussed the fact that  Micron has created an industry group to collaborate on the implementation of an open interface specification for a new memory technology called the Hybrid Memory Cube (HMC). [http://www.hybridmemorycube.org/]

    The HMC is a stack of multiple thinned memory die sitting atop a logic chip bonded together using TSV. This greatly increases available DRAM bandwidth by leveraging the large number of I/O pins available through TSVs. The HMC requires about 10% of the volume of a DDR3 memory module. It is claimed that the technology provides 15X the performance of a DDR3 module, uses 70% less energy per bit than DDR3 and uses 90% less space than today's RDIMMs. [see IFTLE 95 "3DIC - Time Flies When You're Having Fun; Further Details on theMicron HMC..."; IFTLE 74 "The Micron Memory Cube consortium"]

    The HMC device uses TSV technology and fine pitch copper pillar interconnect.  The DRAM logic, responsible for DRAM sequencing, refresh, data routing and error correction is placed in a  separate high performance logic die.  DRAM and logic are connected by thousands of TSV. The DRAM is a slave to the logic layer timing control.  The HMC was constructed with 1866 TSVs on a roughly 60um pitch. 



    HMC electrical performance is are compared to other DRAM modules below.

    

    TI Studies Impact of TSV Stress on Electrical Performance

    They found that the impact of TSVs on surrounding Si is tensile but that a tensile etch stop layer (ESL) counters the impact of the TSVs on near-surface Si where devices are present. Also, insertion of compressive shallow trench isolation (STI) between the TSV and device will also act to buffer this impact.
    They conclude that "...the electrical properties of N/PFETs between 4 and 16um of TSVs are negligibly impacted (less than 2.3%)..." and that For Wide-IO Memory-Logic interface applications employing a 40 x 50 um JEDEC TSV array, ESD and decoupling capacitors which do not contain N/PFETs can be placed immediately adjacent to TSVs such that CMOS logic circuitry does not require placement less than 4 um.
    CFL Fails While Incandescent Lester Still Going Strong

    When last we discussed our hero Lester the incandescent lightbulb [ see  IFTLE 98 "Lester the Lightbulb vs CFL and LED: the Saga Continues"] we found out that an actual calculation of the cost of various electrical functions in my household revealed that lighting was responsible for $4.31 per month (that’s for operating 30 bulbs) on your electric bill and that saving three-quarters of that by using Lester's lighting cousins CFL or LED would therefore save you about $36/year (if you replaced all 30 bulbs), which is not enough to buy you 1 LED bulb. The CFLs whose price was now down to about $4 each (vs $0.25 for Lester)  promised 9.1 years of lifetime (at 3 hrs use per day). Our test bulbs (CFL and LED) were installed on 08/15/2011 [ see IFTLE 63 "Bidding Adieu to Lester Lightbulb"]. So...cousin CFL lasted less than 11 months (vs the promised 9.1 years). I guess you’d have to call this an "outlier"?
    So cousin CFL operated 11 months saving me 1/30 of $4.31 or 14 cents / month or $ 1.54 in 11 months …but remember the bulb cost me $3.97 . You can do the math. And remember since the CFL’s contain mercury, I’m now supposed to contact the EPA for proper disposal instructions (yeah right !) 
    Cousin CFL and cousin LED promised me "hope and change"...  "to transform US power consumption as we know it today." So far, I'm down $2.43 and need to replace the bulb. Typical Govt BS !
    I guess we can understand now why the Govt. got involved to ban poor Lester from the shores of the US. Would anyone actually buy these CFL or LED bulbs, unless they were forced to ?
    Cousin LED is still burning bright as are all the incandescants that were started at the same time. Be assured we will keep you up to date on cousin LEDs health !
    For all the latest on 3DIC and advanced packaging stay linked to IFTLE.............................

    TI researchers have used NanoBeam Diffraction (NBD) to measure near-TSV Si strain in fully processed wafers. The electrical behavior of poly-SiON P/NFET transistors were characterized for full thickness wafers varying temperature, orientations and proximities to isolated and arrayed TSVs.
    NanoBeam Diffraction measurements of Si strain within 5 um of TSVs were acquired for samples prepared from fully processed wafers, showing that for proximity greater than 1.5 um the impact of TSVs is negligible.

    IFTLE 108 2012 ECTC 2: NCF, WUF, MUF for tight pitch Assembly

    July 1, 2012 12:46 PM by Garrou

    For those of you paying attention, you will have noticed that IFTLE has been stuck on 107 for nearly a month.

    Has all progress stopped in 3DIC ?.....NO

    Has all progress stopped in Advanced packaging ?......NO

    Are there no new industry rumors  ?......NO

    So whats up IFTLE where is our new information ???

    It's as simple as IT issues at the main SST server....boring ....but true.

    Now that we are back up:

    Lets catch up with technical highlights of the 2012 ECTC Conference.

    Wafer Underfill processing (NCF)

    Toray presented results of their study on suppressing wafer level underfill (WUF) material entrapment at copper pillar/Pad joints.  The NCF was laminated on the wafer and then the surface was planarized by the bit cutting technique.  Chips are then bonded to cu/Ni/Au pads.

    (Click on any of the images below to enlarge them.)



    When the top chip and lower chip are joined the temp must be raised slightly (sticking process) to get the NCF to flow together. This holds the two chips in place.


    Factors Controlling NCF
    Namics reported on the parameters controlling NCF performance. One of the main issues with NCF has been voiding. Namics reports that one of the causes of voids is captured air which is generated when an IC connects to NCF. This relates to the flow of resin. They could decrease the voids by optimizing the minimum melting viscosity. Another type of void comes from volatilization of gases may occur from organic materials in the structure such as the substrate. They found that the higher minimum melting viscosity is, the more effectively this type of voids can be controlled. They also optimized the minimum melting viscosity, curability and flux-ability for good interconnection. When the minimum melting viscosity is too high, the connection is poor. When cure speed is too high, solder melting is blocked. They attempted to optimize flux activity, and found that gelling time, minimum melting viscosity and oxidation-reduction power need to be controlled.
    Hitachi Chemical (HC) also reported on their attempts to optimize their NCF products. HC reports that The major requirements for processability are (1) NCF can be laminated to the bumped wafer without air trapping around the bumps and dicing lines; (2) In the process of back grinding, the wafer laminated with NCF can be grinded back side (opposite side of NCF) to thinner wafer without damage such as wafer crack and delamination of NCF; (3) the alignment mark or dicing pattern on the wafer can be recognized through NCF; (4) the NCF-laminated wafer can be diced without damage such as chip crack and delamination of NCF.
    Issues and solutions are listed in the table below:


    Compression Molding Compounds for Fan out WLP and MUF

    Hitachi Chemical (HC) reported on their studies on using solid molding compounds for fan out WLP and molded underfill (MUF) . Currently, liquid molding compounds are mainly used for eWLB as encapsulant. Liquid molding compound issues include cost, warpage and high die stand-off caused by molding shrinkage.

    HC shows that solid molding compounds has better wafer warpage results that liquid wafer warpage. Package warpage was almost flat over the temperature range tested.


    High filler content is necessary for such molding compounds. Lower temp curing is also useful to lower warpage due to reduction in thermal shrinkage. Post mold cure is 150C for 1 hr.

    Using solid molding compounds for MUF, flip chips can be molded/underfilled at 130 C / 250 sec.
    Koyanagi-san and co-workers at Tohoku Univ have looked at the sue of NCF and compression molding for 3D integration using self assembling technology. They examined chips with 20 um pitch Cu-SnAg microbumps with bump height ~  6 um ( 3 um thick Cu and 3 um thick SnAg). The chips were self assembled face up on a carrier wafer. Then, the chips were transferred to the corresponding target wafer with microbump-to-microbump bonding through a NCF. The strength of temporary bonding was lower than the microbump bonding through the NCF, and thereby, the chips were removed from the carrier wafer and successfully transferred to the target wafer. After that, the target wafer having the chips bonded upside down on the wafer was packaged by a compression molding technique with a granular resin that covered all over the self-assembled chips to planarize the chip-on-wafer structure. Finally, the chips and the resin were simultaneously thinned from the backside of the chips.


    For all the latest on 3DIC and advanced packaging (hopefully in a week or less) stay linked to IFTLE................

    IFTLE 107 2012 ECTC Part 1 Committees and Awards

    June 24, 2012 4:19 PM by Garrou

    The 2012 IEEE ECTC conference was held, as it always is, over Memorial Day weekend this year in San Diego. Attendance was an outstanding 1200+.
    The executive committee, which is responsible for all content,  is shown below. (Click on any images to enlarge them.)


    [Back row: Steve Bezuk, Pat Thompson, Wolfgang Sauter, Beth Kesser (winner of the IFTLE  name the packaging experts contest !), Bill Moody, Sunil Peking, Alan Huffman, Tom Reynolds                          Front row: Eric Perfecto, Jean Trewhella, Kitty Pearsall, Dave McCann, Rajen Dias, Lisa Renzi]
    The committee gave special thanks to two wives who have been helping with registration and anything else the conference needed for over a decade -- Lynn Reynolds and Nadine Bezuk:

    IEEE CPMT AWARDS
    An important part of every ECTC is the IEEE CPMT awards ceremony. This year's CPMT officers include : Ricky Lee (President); Jie Xue (Technical VP); Jean Trewhella (VP Conferences); Kitty Pearsall (VP Education); Wayne Johnson (VP Publications) .
    The theme of this year's meeting was "going on safari" (I assume tied to the San Diego Zoo) so that's a safari hat on Ricky's head in case you're wondering.
    This year's award winners included:

     IEEE CPMT Field Award to Dr. Mauro Walker (Motorola - Retired)
    As IFTLE has described previously, the Field award is the highest level award in IEEE for any given division, so this is the highest award available in the world for IC packaging. This year's recipient Mauro Walker has had a long career of accomplishment in the advancement of electronic manufacturing and manufacturing technology in industry, academia and professional societies. His leadership in Motorola in the 1970s and 1980s drove the component packaging miniaturization that was necessary for portable communications such as cell phones pagers and two way radios. He established advanced manufacturing technology centers within Motorola which developed many innovations for high speed surface mount assembly.
    He is the previous recipient of the IEEE's Special Manufacturing Technology Award and the Society for Manufacturing Engineers' "Total Excellence in Electronic Manufacturing Award." Walker is an IEEE fellow and founder of the IEEE International Electronic Manufacturing Technology Symposium (IEMT).
    Having worked on technology introduction programs with Motorola during this time, I can tell you that this is a well deserved award. There was no one introducing technology like bumping and chip scale packaging into consumer products better or earlier than Motorola in those days.  Congrats Mauro!
    IEEE CPMT Dave Feldman Award to Dr. Phil Garrou (Microelectronic Consultants of NC)
    The Dave Feldman award is for extended and extraordinary leadership in the IEEE CPMT society. It is named after Dave Feldman who was a key player in Bell labs in the 1950 and 60s and started the ECC (the predecessor  to ECTC) in 1950. I am humbled to say that this year's winner was yours truly. After the luncheon, a bright eyed 20 something engineer came up to me and asked exactly what you had to do to win an award like this, i.e what made me stand out from the other folks in a position of leadership in this large organization. He probably expected some quick cliche answer, but instead I bent his ear with some philosophy. But seriously, the two actions that I am most proud of during my Presidency have to be (1) installing 1 man one vote on a global basis. While Rao Tummala certainly drove the global expansion of the CPMT society during his 4 years, when I took over as President our board of Governors still had a European and an Asian representative which the rest of the US elected body "selected" to represent the non US members. After developing enough internal consensus,  I pushed to have non US members select only their own representatives and to have each region represented based on the number of members in those regions. Seems logical enough, but somebody had to actually push to get it done and that was me. FYI - it is no coincidence that our last president was from Germany and our current president is from Hong Kong - we are now truly a global society which was Rao and my original dream. PS - growth in both these areas continues - this year both Europe and Asia representation went up by one BOG member while the US went down by two. (2) the complete ownership of the ECTC. Since I started going to the ECTC in the mid 1980s, I was always confused by the co-ownership (IEEE CPMT and EIA) that existed. As I took over as President this did not clarify itself, but rather became more and more confounding. ECTC was, and is the flagship conference of the CPMT, but it was only partially controlled by our IEEE organization. So my second "quest" was to buy out the EIA. I was not able to conclude this during my term, but after convincing incoming President Bill Chen of the logic in this, we moved forward during his presidency to amicably conclude this transaction. That's it, although it may seem trivial to you the reader, that's what I think my lasting stamp on the organization will forever be. 

    Sustained Technical Contribution Award - Tseung-Yuen Tseng (Chiao-Tung Univ Taiwan)
    The sustained technical contribution award went to Tseung-Yuen Tseng of National Chiao-Tung Univ in Taiwan where he is University Chair Professor in the Department of Electronics Engineering and the Institute of Electronics. Dr. Tseng's professional interests are electronic ceramics, nanoceramics, ceramic sensors, high-k dielectric films, ferroelectric thin films and their based devices, and resistive switching memory devices. He has published over 300 research papers in refereed international journals. He invented the base metal multilayer ceramic capacitors, which have become large scale commercial product. Dr. Tseng was elected a Fellow of the American Ceramic Society in 1998, IEEE Fellow in 2002 and MRS-T Fellow in 2009.

    Exceptional Technical Achievement Award - Andrew Tay - National Univ of Singapore
    Electronics Manufacturing Technology Award - Chin Lee - Univ of California
    Outstanding Young Engineer Award - Mudasir Ahmad - Cisco
    IEEE Fellows - Mao Jun Fa (china), Yogendra Joshi (USA), Pradeep Lall (USA), Mike Li (USA), Anthony Oates (Taiwan), William Palmer (USA), Enboa Wu (China)
    For all the latest on 3DIC and advanced packaging stay linked to IFTLE....................
































    IFTLE 106 2012 Symp on Polymers for Microelectronics

    June 16, 2012 2:43 PM by Garrou

    This was the 15th year that polymer suppliers and users have met in Wilmington DE to discuss the latest advances in polymeric materials. All of the big boys were there including : HD MicroSystems , Dow, JSR, Asahi Kasei, Toray, Nippon Kayaku (MicroChem), AZ and Hitachi Chemical.
    Certainly the most interesting bit of information that I learned about a materials supplier was that Alpha started its business in 1704 making cannon balls... cannon balls to solder balls -- now that's a roadmap for miniaturization!

    Certainly the main theme, as you shall see below, was the development of low curing temperature polymers that could come close to matching epoxies curing temp (i.e ~175C) while maintaining improved thermal and mechanical properties.   
    My plenary presentation was based on the new Yole report "PolymericMaterials for 3DIC & WLP Applications"

    Basically over the last 50 years the industry has developed five  basic chemistries for the microelectronics industry. In chronological order they would be epoxies, siloxanes, polyimides, BCBs and PBOs.

    (Click on any of the images below to enlarge them.)

    If we look at the properties that are important to all or most functions / applications we find 4 broad categories including electrical, mechanical, thermal and misc. (other).

    The half dozen key functions that we want these polymers to fill and the seven wafer level applications that we are looking to use them in are depicted below.
    


    Yole projects a 26% CAGR for WL applications over the next few years which will expand the current market to near $1B with significant expansion of applications other than FC bumping.
    Since new materials take decades and 10s of millions of dollars to develop, those in the business of wafer level packaging over the next 5-6 years will basically have products from these 5 chemistries to serve the functions for the listed applications.  
    


    The theme for permanent dielectric suppliers at this meeting seemed to be positive tone aqueous developable dielectrics with sub 200C curing temperatures and resultant low stress. The newer packaging scheme such as eWLB require this evolution in dielectric materials because the wafer substrate is epoxy based and  cannot survive the processing temperatures needed to cure polyimides or most PBO and BCB materials. Also, ICs with embedded memory are very sensitive to process temperatures and survivability drops dramatically with increase in temperatures. Lastly, advanced technology nodes such as 32 and 22 nm use lower-k dielectric materials, which are sensitive to the high stresses generated by higher curing temperatures.
    Toray is offering a LT series low-temperature curing,  positive-tone photosensitive PI coating with a 170- 200C curing temp and resultant 13 MPa thermal stress. With a tensile strength = 100 MPA, elongation of 30% and Modulus of 2.5 GPa . While the residual stress is reported as 13 MPa, the CTE is troubling at 70 ppm. Asahi Kasei is offering  BM series PIs which reportedly can cure as low as 200C with a Tg of 220C, a CTE of "50-60" and a stress of 19 MPa . HD Micro reported on a new PBO, 8850, with reported better chemical resistance, which can be cured at 250C. JSR reported on their WPR series dielectrics which for positive tone are cresol based with rubber reinforcement. While they can be cured at 200C and have low residual stress ( 20 MPa), their tensile strength (80 MPa) and elongation (7%) are low for permanent dielectrics.  Dow chemical reported on their aqueous developable P6505 BCB which cures as low as 180C (3 hrs) with a resultant stress of 25 MPa. Most of the properties look like the BCB 4000 series with a notable exception that water absorption has risen from 0.2% to 2% for the new version. 
    Toray also introduced a siloxane product to replace acrylics for optical applications such as CMOS image sensors, LCD and OLED displays and solar modules. It is 99% transparent at 400 nm and is much more thermally stable than the typical acrylics.
    As a general comment, all of these materials are beginning to look like one another which may or may not be a good thing for the industry. As IFTLE has said many times before, you must determine what properties are most important for your application and choose your dielectric accordingly. 
    Next week we begin our coverage of the ECTC conference. For all the latest in 3DIC and advanced packaging stay linked to IFTLE......................
    

    IFTLE 105 TSMC Tech Symp; UMC Investment; Latest rumors on IBM, Intel, Samsung and Apple

    June 9, 2012 8:53 AM by Garrou
    TSMC Tech Symp

    At the 2012 TSMC Tech Symp in April they revealed Reference Flow 12 which shows 2.5/3D firmly entrenched in the TSMC roadmap.
    Recent blogs have discussed TSMCs move into the 3D and advanced packaging area. [see IFTLE 94 “Experts discuss InterposerInfrastructure at IMAPS DPCand IFTLE 102 “3.5D interposer technology could somedayreplace PCBs" -- TSMC's Doug Yu” ]
    Indeed TSMC isnow showing slides where only the memory and substrates are coming from external sources, making them a turnkey solution for what they are now calling 3.5D [link].


    UMC stays in the game
    In IFTLE 88 “Apple 2.5D Rumors; Betting the ranch…” we drew an analogy of putting new fab production in place to a poker game in the Wild West – or betting the ranch. Well, the recent announcement by UMC certainly had them tossing their chips into the center of the table matching the recent capacity announcements by TSMC and Global Foundries. The UMC 300mm Fab 12A Phase 5 & 6 in Tainan will extend 28nm production. P5 & P6 will provide advanced 28nm, 20nm, and 14nm capacity, and is scheduled for equipment move-in during the second half of 2013. Total cleanroom area is 53,000m2 and will be capable of 50K wafers per month, bringing total monthly design capacity for Fab 12A to 130K wafers. With the planned P7 & P8, the eight phase fab complex will have a total design capacity of 180K wafers per month.
    Cumulative capex for UMC's Fab 12A phases 1-4 is projected at $ 8 billion, with P5 & P6 to add nearly $ 8 billion more. There are further plans for P7 & P8. As we said earlier, only the big time players are sitting at this table. With such investments, UMC is certainly showing that they intend to stay in the game.
     They also announced continued activity in “… BSI CMOS image sensor, 2.5D interposer, and 3D IC TSV to provide a truly comprehensive, leading foundry technology platform”  
    Rumors from the ECTC
    The IEEE ECTC meeting was last week and for those of you who are unaware, it is the number one show for advanced packaging in the industry. 2.5/3D has grown steadily at this conference and it now appears to be nearing 50 % of the ECTC content [ 50% of 6 parallel sessions for 2.5 days] . There were no major announcements at the meeting, but there were some interesting rumors. My filtering criteria is that I must hear the rumor at least twice from separate sources before I report it on to you.  None of these could be substantiated by the parties involved, but that is not surprising.
     IBM Power8 processor
    IFTLE has reported before that rumors were swirling that a future generation of the IBM power chip processor would be using a 2.5D interposer configuration. Very strong, multisourced rumors at ECTC persist that the Power8 is currently undergoing testing in IBM servers and we could be hearing about this major interposer announcement “soon” .
     Intel
    If your like me, you have been waiting for 5+ years for the imminent 3D announcement from Intel. Recall that we have been told that the technology is ready but it would be up to the product departments as to when to introduce it. Well, not so good news here. The rumor going around is that we are probably looking at 2017 when 450 is introduced. (Don’t shoot me I’m just reporting the rumor. ) If anyone from Intel would like to deny this and give IFTLE better information please send me an email.
    Apple / TSMC / Samsung
    Back in IFTLE 88, “Apple 2.5D rumors……” (which I’m told was the most read IFTLE blog of all time) we discussed the fact that TSMC and Samsung are in competition for the next generation , the A6, processor for the Apple iPod, iPad etc.. Although everything is hush, hush, it is clear that TSMC is at least developing prototypes based on their interposer technology. It is unknown whether Samsung is doing the same (but we can hope so).  Two opposing  rumors were making the rounds at ECTC. Rumor 1 had Samsung about to make a 2.5/3D announcement, but rumor 2 had Samsung developing an “unknown technology” that negated the need for TSV and leading them to the conclusion that 2.5/3D would not be needed in the future. The Samsung clamp down on the release on any information on 2.5/3D remains …hermetic . Yes these could in fact be the same rumor, but I, for one, hope not.
    Lots more from the ECTC over the next few weeks……………..
    For all the latest on 3DIC and advanced packaging stay linked to IFTLE……………………………………….

    IFTLE 104 IMAPS DPC Part 2; Over 50% of TI WB Converted to Copper

    June 4, 2012 9:58 AM by Garrou
    Continuing with key presentations from the 2012 IMAPS Device Packaging Conference in Ft McDowell AZ.
    Tezzaron Process Technology
    Bob Patti showed off two Centip3De, a 3-D IC stack using 128 ARM Cortex M3 cores and 256 Mbytes of stacked DRAM from the Univ of Michigan and the 3-D MAPS, a massively parallel processor using 64 custom cores stacked with a block 256 kilobytes of scratch pad memory from Ga Tech. For more details on these see IFTLE 93, "2.5/3D at the 2012 ISSCC".

    (Click on any of the images below to enlarge them.)

    Amkor Discusses 2.5/3DIC


    Amkor's Ron Huemoeller reported that 3D vertical stacking is:

    - memory and application processor driven
    - today focused on 28 nm CMOS and moving to 22 nm
    - application processors are near exclusively moving to OSAT finished wafer process flows
    Whereas 2.5D Interposers are:
    network, CPU and GPU driven
    ........ mother boards reduced from 10 to 6 layers
    ........ reduce chip mask layers
    ........ smaller x, y dimensions
    - focused on large package bodies (40 -90 mm , near retical sized Si)
    -  both foundry and OSAT wafer flow processes being used
     
    He sees both dis-integration of large logic blocks and separation of functions

    - allows focus of specific functions which require  leading process nodes
    - improves wafer yield
    - reduces time to market
    - reduces mask layer count at advanced process nodes
    Concerning the interposer supply chain:
    - laminate (which can theoretically be delivered in large panel format (i.e. 500 x 500 mm ) are being investigated by several "elite substrate manufacturers" [ Unimicron, DNP, Shinko, Kyocera]. Limited to 8 um L/s and 40 um vias on 85 um pads today. 5 um l/s will require stepper and better resists which change the economics. 5 um L/S thought to be many years away. Latency issues will limit adoption as will limitations in va/pad design rules.
    - glass can be delivered in large panel or wafer format. Several glass companies [Hoya, Corning, AGC] are investing in capability to support glass interposer technology. Glass faces challenges for CMP / damascene processing.
    - silicon in 200 or 300 mm several companies supporting silicon interposers in idle foundry space on legacy node technologies. Amkor finds only 3 foundry players committed to delivering "fine featured" interposers [ TSMC, GF, UMC] with TSMC the only one currently delivering in any quantity.
    According to Amkor several foundry sources are interested in manufacturing Si interposers and a couple are already delivering fully functional wafers. Currently design rules  "are aggressive" i.e. less than 2 um L/S and 5 um vias.

    Amkor indicated that the predominant interposer designs are what IFTLE has been calling "fine featured" as follows:

    When looking at TSV products expected to enter the market in the next few years, Huemoeller offered the following roadmap.

    TI Promotes Cu WB
    TI has recently announced that all 7 TI internal assembly and test sites are now converted to Cu WB. 6.5B devices have been shipped in Cu WB with conversions continuing. TI which started their Cu WB studies in 2003 are in HVM at the 65 node and have qualified down to the 45 node. 50% of all their interconnect wire is now Cu.
    Analog, wireless and embedded products in BGA and leadframe packages are all qualified. Cu shows less wire sweep during package molding and since it has better inherent thermal conductivity it shows better battery life. Next TI will be looking at "high rel" applications such as automotive, military and down hole drilling with Cu wirebonding.


    
    For all the latest in 3DIC and advanced packaging stay linked to IFTLE...................

    IFTLE 103 2012 IMAPS AZ Device Pkging Conf; Fujitsu Low Temp Cu-Cu Bonding

    May 27, 2012 8:35 AM by Garrou
    It's been over for a few months now, but IMAPS was a bit slow this year gathering the presentations from their device packaging conference, This is however understandable and excusable due to the untimely death of IMAPS employee Jackie Joyner. So let's begin looking at the 2.5/3D and significant advanced packaging papers.

    SSEC Wet Etch for Via Reveal
    Laura Mauer of SSEC discussed silicon wafer thinning to reveal Cu TSV. The standard via reveal processis shown below. SSEC contends that a KOH wet etch process can be used for the final Si removal without etching the oxide liner. This can be sealed with oxide/nitride and then CMP'ed to expose the Cu vias.

    Wet etch with HF/HNO3 has also been proposed by ASET and shown to have minimal impact on the electrical characteristics of the transistors [link].
    Asahi Glass TGV (Through Glass Vias)
    Takahashi of AGC discussed the fabrication of TSV in glass. They have been able to fabricate TGV with a  193 nm ArF excimer laser by using short pulse width (20-30 ns). The TGV do have significant slope. Better results are achieved when the glass is processed at elevated temperature ( i.e 200C)

    
    Focused electrical discharge can also be used to process TGV in less than 1 ms. AGC claims that there is no physical limit to TGV diameter using electrical discharge. Electrical discharge TGV show smooth sidewalls and rounded via edges. Similar to the laser process the process requires no masks.

    Underfill options - Hitachi, Lord, Dow
    Hitachi Chemical discussed non cnductive pastes and films. Packaging in general is moving towards finer pitch and smaller gaps requiring a change in underfill materials and procedures.  NCP and NCF applicable for fine pitch and narrow gaps. In terms of pad finish, Hitachi notes that Cu with OSP "is more difficult to have a good connection."

    Lord detailed their screen printable NCP ( Tg = 166 C; Mod = 4.1 Gpa) with built in fluxing agent which allows them to do cu-cu bonding on oxidized cu studs. Similarly Dow presented data on their new pre applied underfill (WUF) films with the following materials properties:

    
    Vacuum lamination is preferred and curing is done at 175C for 1 hr. Voiding seen after bonding can be eliminated by pressure curing or optimizing the film thickness. Initial reliability tests indicate good adhesion through MSL-3- 260 C and TCT cond B.

    Fujitsu Low Temp Copper-copper Bonding
    Fujitsu described further advances in their low temp Cu-Cu bonding technology [link].
    Their unique process uses a diamond bit milling machine to achieve a highly uniform and highly polished (7 nm surface vs 210 as plated) which can be thermo-compression bonded at RT and shows grain growth across the interface at 200 - 250C vs 350 C+ for a  standard CMP'ed surface.
    

    

    Underfill and Cu bumps can be simultaneously cut together by diamond bit with no residue on bump, but hybrid copper/underfill interface exposed to formic acid before bonding "could not sustain arranged location during bonding process." However, if the interface is bonded first and then exposed to formic acid, "partially exposed," clearly grain growth occurs as low as 140 C.

    
    For all the latest on 2.5/3D IC and advanced packaging stay linked to IFTLE.........................

    IFTLE 102 “3.5D Interposers to someday replace PWBs” - TSMC; GF engaging with 3D customers; Intel predicts Consolidation

    May 19, 2012 2:48 PM by Garrou
    3.5D Interposers

    At the 15th Symposium on Polymers for Microelectronics held last week in Wilmington DE, TSMC’s Doug Yu, Sr. Dir. of front end and back end technology development,  challenged the current nomenclature for interposers and suggested that the more versatile interposer technology should be called 3.5D instead of 2.5D since it is, and will be, capable of much more than the simple 3D stack.
    The term 2.5D is usually credited to ASE's Ho Ming Tong who ~ 2009 (or even earlier)  declared  that we might need an intermediate step towards 3D since the infrastructure and standards were not ready yet.  The silicon interposer, Tong felt, would get us a major part of the way there, and could be ready sooner than 3D technology,  thus the term 2.5D, which immediately caught on with other practitioners.

    Yu's new position is that interposer technology actually is more versatile and thus should be called 3.5D since it  not only offer a better thermal solution than 3D, but "...can  some day replace most of the high density PC boards." Yu's position is that this modular silicon technology will need minimum low density PCB substrate to connect the functions that have been fabricated on silicon and will be, in essence, the perfect "fab centric" solution. Yu proceeded to show how future smartphones and tablets could be made up of such simple 3.5D silicon modules. More from the Polymers for Electronics meeting coming soon at IFTLE.

    Global Foundries 2.5/3D Announcement

    GLOBALFOUNDRIES has announced the installation of TSV production tools for the company's 20nm technology platform. CTO Bartlett announced that they were  "...engaging early with partners to jointly develop packaging solutions that will enable the next wave of innovation in the industry." The first full flow silicon with TSVs is expected to start running at Fab 8 (Saratoga NY)  in Q3 2012 with mass production expected in 2014. GF is also preparing for  a 2.5D line within its Fab 7 facility in Singapore with a similar time schedule as the 3D line in the United States.

    While arch competitor TSMC has announced a one-stop-shop turnkey line which includes all of the assembly and test steps traditionally handled by the OSATS [see: "TSMCrepeats call for foundry-centric 2.5/3D industry"], GF proposes to handle  TSV fabrication (Cu , vias middle) and other front-end steps while typical backend  processes such as temporary bonding/debonding, thinning, assembly and test will be done by their OSAT partners such as Amkor [ see IFTLE 65 "..... GLOBALFOUNDRIES Packaging Alliance..." GlobalFoundries reports that they will define a PDK with its partners, initially they are looking at 6 um vias on a  40-to-50um pitch.

    Intel agrees - Its all in the Economics

    At the recent Intel analyst day CEO Paul Otellini CEO predicted that the increasing cost of manufacturing in the IC industry would result in consolidation that  will "...only leave two or three companies at the leading edge of chip design." Otellini reports that "Gordon Moore predicted a thinning out of chip fabrication facilities once the cost of a new 200mm wafer manufacturing plant hit $1bn, but he was a little too early."

    With the cost of a 300mm fab expected to exceed $5B at the 28 nm node and  450mm wafer fabs that are projected to cost more than $10B apiece few companies will have enough volume to absorb such costs.  

    Readers of IFTLE know that we have been predicting this outcome for several years [ see PFTLE "IC Consolidation, Node scaling and 3DIC". Nice to see that Intel  agrees, although this will severely limit options for customes of the latest node technologies. 

    If you look at this strictly in terms of economics, HVM players at 22 nm should be limited to :

    Logic - Intel, Samsung, ST Micro
    Memory - Samsung, Toshiba, Micron/Elpida, Hynix ?

    Foundries - TSMC, GF

    That's less than 10 total players on the leading edge moving forward. Better start getting used to it !

    For all the latest on 3DIC and advanced packaging stay linked to IFTLE...................

    IFTLE 102 ��?3.5D Interposers to someday replace PWBs��? - TSMC; GF engaging with 3D customers; Intel predicts Consolidation

    May 19, 2012 2:48 PM by Garrou
    3.5D Interposers

    At the 15th Symposium on Polymers for Microelectronics held last week in Wilmington DE, TSMC’s Doug Yu, Sr. Dir. of front end and back end technology development,  challenged the current nomenclature for interposers and suggested that the more versatile interposer technology should be called 3.5D instead of 2.5D since it is, and will be, capable of much more than the simple 3D stack.
    The term 2.5D is usually credited to ASE's Ho Ming Tong who ~ 2009 (or even earlier)  declared  that we might need an intermediate step towards 3D since the infrastructure and standards were not ready yet.  The silicon interposer, Tong felt, would get us a major part of the way there, and could be ready sooner than 3D technology,  thus the term 2.5D, which immediately caught on with other practitioners.

    Yu's new position is that interposer technology actually is more versatile and thus should be called 3.5D since it  not only offer a better thermal solution than 3D, but "...can  some day replace most of the high density PC boards." Yu's position is that this modular silicon technology will need minimum low density PCB substrate to connect the functions that have been fabricated on silicon and will be, in essence, the perfect "fab centric" solution. Yu proceeded to show how future smartphones and tablets could be made up of such simple 3.5D silicon modules. More from the Polymers for Electronics meeting coming soon at IFTLE.

    Global Foundries 2.5/3D Announcement

    GLOBALFOUNDRIES has announced the installation of TSV production tools for the company's 20nm technology platform. CTO Bartlett announced that they were  "...engaging early with partners to jointly develop packaging solutions that will enable the next wave of innovation in the industry." The first full flow silicon with TSVs is expected to start running at Fab 8 (Saratoga NY)  in Q3 2012 with mass production expected in 2014. GF is also preparing for  a 2.5D line within its Fab 7 facility in Singapore with a similar time schedule as the 3D line in the United States.

    While arch competitor TSMC has announced a one-stop-shop turnkey line which includes all of the assembly and test steps traditionally handled by the OSATS [see: "TSMCrepeats call for foundry-centric 2.5/3D industry"], GF proposes to handle  TSV fabrication (Cu , vias middle) and other front-end steps while typical backend  processes such as temporary bonding/debonding, thinning, assembly and test will be done by their OSAT partners such as Amkor [ see IFTLE 65 "..... GLOBALFOUNDRIES Packaging Alliance..." GlobalFoundries reports that they will define a PDK with its partners, initially they are looking at 6 um vias on a  40-to-50um pitch.

    Intel agrees - Its all in the Economics

    At the recent Intel analyst day CEO Paul Otellini CEO predicted that the increasing cost of manufacturing in the IC industry would result in consolidation that  will "...only leave two or three companies at the leading edge of chip design." Otellini reports that "Gordon Moore predicted a thinning out of chip fabrication facilities once the cost of a new 200mm wafer manufacturing plant hit $1bn, but he was a little too early."

    With the cost of a 300mm fab expected to exceed $5B at the 28 nm node and  450mm wafer fabs that are projected to cost more than $10B apiece few companies will have enough volume to absorb such costs.  

    Readers of IFTLE know that we have been predicting this outcome for several years [ see PFTLE "IC Consolidation, Node scaling and 3DIC". Nice to see that Intel  agrees, although this will severely limit options for customes of the latest node technologies. 

    If you look at this strictly in terms of economics, HVM players at 22 nm should be limited to :

    Logic - Intel, Samsung, ST Micro
    Memory - Samsung, Toshiba, Micron/Elpida, Hynix ?

    Foundries - TSMC, GF

    That's less than 10 total players on the leading edge moving forward. Better start getting used to it !

    For all the latest on 3DIC and advanced packaging stay linked to IFTLE...................

    IFTLE 101 Advanced Packaging at IMAPS MINIPAD part 2

    May 13, 2012 8:15 AM by Garrou
    Continuing with our examination of advanced packaging at the 2012 IMAPS MINIPAD.

    ST Micro reported on stress induced fine pitch copper pillar failures. Compared to solder bump, Cu pillar bumping is known to possess good electrical properties, better electromigration performance and better thermal fatigue resistance . The only drawback is that Cu pillar bump can introduce high stress due to Cu higher stiffness compared to the solder material. Therefore, the stress induced failures become a major issue when Cu pillar bump is built on low k or extreme low k (ELK) chips. In this ST Micro study, fine pitch copper pillar has been assessed vs polyimide effectiveness for fine pitch Cu pillar interconnections having small pillar diameter.

    (Click on any of the images below to enlarge them.) 

    Vehicle1 (package 2 configuration) used extreme lowk ILD materials. Die were attached on the substrate without underfill and underwent several die attach reflow cycles to induce failure and define the more robust configuration. The no PI leg did not evidence any defect up to 20 reflows but the PI passivated leg showed 100% failure after 20 reflows which appear to be stress induced failures ( likely to be crack in aluminum pads ).

    
    Results after reliability tests show that the implementation of polyimide for fine pitch Cu pillar is not obvious. Thus, in the case of PI configuration, failure analysis reveals three main failure modes: delamination at the Bump/PI/pad and copper stress voiding in the pad metal in stacked vias structures, both occurring during thermal cycles. Delamination in the low-k layers has been also found for the highest die size in the PI configuration. All those analyses have revealed that for the tested configurations, higher stress has been observed with the PI configuration compared to the no PI one.

    FEA was done to better understand these results. In the No Polyimide configuration, the stress is spread along the pad structure thanks to the higher copper contact. Indeed, the passivation layers (i.e. SiN and PSG layers) have sufficient mechanical properties to transfer the stress to the beneath layers. In the PI configuration, high peak stress is observed beneath the Copper/Aluminum interface. On the contrary, in the No PI configuration, the stress is spread along the pad structure thanks to the higher contact of Copper pillar bump.

    STATSChipPAC looked at some "Advanced Ultrathin eWLB-PoP solutions." eWLB has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. There is also great opportunity related to a 3D variation of eWLB which would allow for mounting of components or another package on the top surface with thinner profile and PoP (Package-on-Package) technology.

    The table below shows reliability for such stacked test vehicles.


    Bernd Appelt of ASE continued the theme of thinner is better with his presentation "Ultra Slim Packages with Ultra Slim Substrates" There is no question as the figure below shows devices continue to get thinner.
    

     JEDEC package heights are defined as follows:

    
    The ASE package family fits these dimensions as follows:


    Substrate thickness vs package thickness are shown on the following chart:

    The ASE embedded technology a-EASI (adv embedded assembly solution integration). They are undergoing customer evaluation with embedded actives and passives.


    FCI presented the latest n their ChipletT(TM) and ChipsetT(TM) embedded die fan-out packaging based on multilayer flex. We discussed this technology in detail last fall [see IFTLE 83, "Orange County 3DIC Workshop"]
    Below we see a nice example of what can be done with this technology, i.e a 50% reduction in footprint by embedding the ASIC die.
    

    

    


    For all the latest in 3DIC and advance packaging stay linked to IFTLE......................

    IFTLE 100 IMAPS MINAPAD Addresses Advanced Packaging in Grenoble

    May 6, 2012 8:30 AM by Garrou
    "I've been a big fan of Phil's ever since his first blog in August of 2007. Did you know he was born in Hell's Kitchen in New York City? Congratulations to the world's foremost expert on 3D integration on his 100th blog!" -- Peter Singer, Editor-in-Chief, Solid State Technology

    Dr. Phil Garrou has been blogging for years on the evolution of semiconductor assembly and packaging technologies. In his first 100 blog posts, he's covered the emergence and explosion of 3D packaging, and most recently, the "2.5D" innovation of interposers.

    To celebrate Dr. Garrou's 100th post to Insights from the Leading Edge, we've compiled a list of his top 10 best-read recent blogs. You'll find them at the end of this post..................

    IMAPS France held the 2nd Micro/Nano-Electronics Packaging, Assembly, Design and Manufacturing Forum (MiNaPAD) in Grenoble in late April.

    Jean-Marc Yannou, President of IMAPS France gave a Yole market update on 3DIC and TSV interconnects indicating that Wafer-level-packages are the fastest growing semiconductor packaging technology with more than 27% CAGR in units and 20% in wafers over the next 5 years to come.

    (Click on any of the images below to enlarge them)

    Yannou also repeated rumors that "Power 8 by IBM believed to be based on 3D interposers; Haswel, Intel GPU on 2.5D interposers for laptops with lots of on board memory and ultra large data bus. "
    Leti gave an update on the 3DICE program being done under the European Unions 7th Framework with partners Datacon, Disco, EVG and ST Micro. Below find the unit operations that are part of the program and those responsible. They have concluded that B2F has less operations and is easier to accomplish than F2F.

    Back to face attach can be done with die attach film, full sheet bonding layer or patterned bonding layer.

    B2F pick and place with a Datacon 2200 can reportedly handle 20um thick die with 7um accuracy in 3 sec. Plasma stress relief allows for thin die handling by increasing die strength.

    Thin die encapsulation can be accomplished in several ways i.e by conformal CVD deposition (oxide or parylene), by spin/spray coating of solutions (BCB, PI, ALX) or by film lamination. Die are bevel cut at 45 degrees to make subsequent metallization easier.

    Thermo-mechanical stress in these combinations were examined.






    EVG gave more details on the release process for their ZoneBond TB/DB (temp bond/debond) process.
    

    - Adhesive ring dissolution is enhanced by magasonics                                                                                   
    - Low force, room temperature separation                                                                                                        
    - Compatible with both glass and Si carriers                                                                                                       
    - Adhesives are (solvent)cleanable                                                                                                                    
    - Platform enables use of a wide range of materials, i.e. ZoneBond Open Platform

    The anti sticking layer showed a temperature stability up to 300C for 20 min. Carrier wafers were bonded and debonded 25x.

    Rolf Aschenbrenner of the Fraunhoffer IZM made an in depth presentation on "Molding
    technologies  - A new way for system integration" specifically looking at options for today's transfer molding and compression molding technologies.
    

    While transfer molding has been used for years to make plastic packaged parts, compression molding has recently become in vogue as part of the embedded chip technology package, i.e molded reconfigured wafers.
    

    They propose the following roadmap for system integration with molding.
    

    ST Micro presented some electromigration details on SnAgCu interconnect for WLB packages.
    They find that:
    - IMC induces resistance increase right after stress beginning
    - Electrical open is due to voiding in solder, at Cu3Sn interface, after Cu6Sn5 disappeared
    Since the electrical opens are due to voids at the RDL/solder interface a solution is to insure that the enclosure around the solder ball is large enough and increase the RDL thickness as much as possible.  
    

    We will have more MINAPAD review in next week's IFTLE.

    For all the latest in 3DIC and Advanced Packaging stay linked to IFTLE..........................

    10 Must-Read Insights from the Leading Edge:
    1. Apple and TSVs, top chip makers, and "betting the ranch"


    This post investigated Apple's possible move to TSVs for its A6 chip, and compared capex numbers to the Western trope of "betting the ranch." Apple's semiconductor roadmap, and the advanced packaging technology of TSVs combined for a compelling read. Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2012/02/iftle-88-apple-tsv-interposer-rumors-betting-the-ranch-tsv-for-sony-ps-4-top-chip-fabricators-i.html

    2. LED market is about to explode

    While Insights from the Leading Edge covers a great deal of 3D packaging news, that doesn't mean that there are no other very significant packaging evolutions and market opportunities going on at the same time. Certainly the LED space is one of those, Dr. Garrou said, and readers agreed.

    Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/11/iftle-75-led-market-is-about-to-explode.html

    3. Bidding Adieu to Lester Lightbulb

    Lester Lightbulb has become something of a favorite character on Insights from the Leading Edge, as Dr. Garrou carries out an in-home energy/cost savings analysis of conventional incandescent lightbulbs, CFLs, and LEDs.

    Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/08/iftle-63-bidding-adieu-to-lester-lightbulb.html

    4. Advances in CMOS Image Sensing

    In the fall of 2007, Toshiba first announced the commercialization of TSV in a CMOS image sensor (CIS). The next step of circuit repartitioning and stacking was interrupted by back side imaging, which flipped the chip over and let the light enter through the least obstructed side to let more light in per pixel. Now, we consider today's CIS advances.

    Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2012/02/iftle-89-advances-in-cmos-image-sensing.html

    5. Cell Phones and Memory Consolidation

    The cellphone continues to pull in the functionality of digital cameras, PDAs, GPS navigators, mobile TV and numerous other applications. It is quickly becoming the dominant market driver for virtually all of these functions.

    Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/10/iftle-69-cell-phones-and-memory-consolidation.html


    6. How Xilinx fit 6.8B transistors on its 2.5D FPGA

    Garrou reviews Xilinx's new FPGA, with 10,000 connections on a silicon interposer, using "2.5D packaging."

    Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/10/iftle-73-xilinx-shows-2-5d-virtex-7-at-imaps-2011.html

    7. MEPTEC 2.5, 3D and beyond

    Reporting from MEPTEC and SEMI's "2.5D, 3D and Beyond Bringing 3D Integration to the Packaging Mainstream" Conference in 2011, Dr. Garrou shares highlights from Amkor, GLOBALFOUNDRIES, and other presenters.

    Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/11/iftle-77-meptec-2-5-3d-and-beyond.html

    8. Fine Pitch Microjoints, Cu Pillar Bump-on-Lead, Xilinx Interposer Reliability

    Dr. Garrou looks at packaging activities at the 2011 ECTC, including presentations from Qualcomm and STATS ChipPAC, Fraunhofer IZM, Xilinx (interposers!), and others.

    Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/07/iftle-58-fine-pitch-microjoints-cu-pillar-bump-on-lead-xilinx-interposer-reliability.html

    9. TSV from 1999 to today, and more on the Micron HMC

    Dr. Garrou shows us the evolution of TSV from 1999 through to today, checks in on MU's HMC, and analyzes some recent packaging news.

    Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2012/04/iftle-95-3dic-time-flies-when-you-re-having-fun-further-details-on-the-micron-hmc-equipment-su.html

    10. Defining 3D, and Canon's packaging equipment foray

    Garrou explains the variety of 3D packaging terms with a little help from "Raymond J. Johnson Jr." He also notes Canon's back-end equipment entry.

    Link: http://www.electroiq.com/blogs/insights_from_leading_edge/2011/08/iftle-62-3d-and-interposers-nomenclature-confusion-equipment-market-shift-to-pkging-continues.html

    Here's to 100 more Insights from the Leading Edge blog posts!

    IFTLE 99 Electronic Design Process Symp (EDPS) focuses on 3DIC

    April 30, 2012 10:26 AM by Garrou
    A few weeks ago EDPS (the Electronic Design Process Symp) held a 3D day in Monterey CA. Riko Radojcic of Qualcomm gave a plenary on the “Roadmap for Design and EDA Infrastructure for 3D Products” and Arif Rahman, Altera, Steve Pateras, Mentor, Mac Greenberg and Bassillos Petrakis of Cadence followed in a session chaired by Herb Reiter of eda2asic, with  presentations on design and test challenges.

    Qualcomm
    Radojcic showed the following Xsect as what is becoming “mainstream technology” consistent with what the recent IMAPS DPC panel had to say [see IFTLE 94, “Experts Discuss Interposer Infrastucture at IMAPS Conference”] with 5 x 50 Cu TSV and solder capped copper pillar interconnect.

    (Click on any of the images below to enlarge them)

    It was good to hear Radojcic comment that “there are no intrinsic process technology show stoppers for memory on logic “ and that we just needed to get into volume production so we could exercise the processes.
    For memory on logic he proposed the following as the status of the design environment:

    Although Qualcomm has publically stated many times in the past that they ae not fans of interposers since they will increase the size of the devices while adding cost (amongst other things), Radojcic offered the following interposer challenges:
    - low cost with fab like (1um pitch) routing may be hard
    - timing driven routing may be had
    - pre stack test may be hard

    - managing Si with floating substrate may be hard

    - fitting a small form factor at system level may be hard

    Altera
    Rahman’s talk for Altera centered on EDA needs for FPGAs. Altera had recently announced a program with TSMC to develop   heterogeneous 3D solutions that would combine an FPGA with a customer’s intellectual property, ranging from CPUs, ASICs,  ASSPs,  memory and optics.


    TSMC is providing the end-to-end CoWoS (Chip-on-wafer-on-substrate -- the internal TSMC name for their 2.5D process) process, including the front-end manufacturing of the die and the back-end assembly and test of the bare die on an interposer with TSVs connecting the bare die.
    The Altera/TSMC team have developed a heterogeneous 3DIC test vehicle for this program.






    Cadence

     
    The theme for Bansal and Greenberg of Cadence was that “Wide-IO is driving 3DIC TSV”

    We have discussed the easoning behind and the status of wide IO in the past [see IFTLE 87, “JEDEC wide IO standards...”] . Bansal shows a nice roadmap for future wide IO standards, and shows  

    why wide IO will be needed in future products:

    They conclude that Cadence stands ready with EDA tools and IP to enable your TSV designs with real experiences and partnerships with ~8 test chips and 1 production chip already completed.
    We have discussed the Cadence [see IFTLE 72 “2011 IEEE 3 Test Wokshop”] and Mentor Gaphics DfT [see IFTLE 83, "Orange County 3DIC Workshop"] work on DfT previously. At EDPS both Bassilios (Cadence) and Pateras (Mentor) further discussed evolving BIST and other test flows for 3DIC.  I suggest you go to their respective web pages for complete detail on these important  test options.
    Follow up on Lester the Lightbulb
    These supportive messages were sent to me following last week's blog:
    "I started keeping receipts and writing down the dates on CFL bulbs I have purchased and so far have received three free replacements from the manufacturer as they tend to die in about a year [like incandescants] instead of 8000 hrs. This may in fact be the true savings to savvy consumers, as I may never have to buy another bulb again!!!"
    “Thank you for being one of the 'voices of reason' in the LED debate.”
    .........................
    For all the latest on 3DIC and advanced packaging stay linked to IFTLE...........

    and proposed that the following gaps currently exist.

    IFTLE 98 Lester the Lightbulb vs CFL and LED : the Saga Continues

    April 21, 2012 4:12 PM by Garrou
    In IFTLE 63 [ see IFTLE 63, “Bidding Adieu to Lester Lightbulb] back in Aug 2011 IFTLE attempted to make the case that our little 25 cent friend Lester the incandescent bulb had gotten a bump rap as he awaited extinction on death row.

    It’s not that the claims of the newer technologies (CFL and LED) using less power than incandescent bulbs are invalid, but rather what appears to be the  bold faced lie that their much greater cost is  compensated by their decades long  lifetimes that upsets all Lester supporters.

    My initial rant and my follow up comments [see IFTLE 82 “3DIC at the 2011...LED testing update”] tried to point out that the testing procedures were highly skewed to make things look like these new technologies were producing bulbs that would last forever. The main issue for me was that the other components found in teardowns of the LED bulbs certainly were not built to survive the LED lifetimes that were being claimed and the new bulbs will only last as long as their weakest component.

    Our installed test LED and CFL bulbs  have now cleared 650 hrs of use. Only 24,000 more hrs to go to meet specs !

    First a little update on pricing as of March 2012. The CFL are down to $4 each as shown below. They are still promising 9.1 years lifetime while using ¼ the power of an incandescent bulb. Oh yes, another minor issue is that when the do burn out it is recommended that you visit the EPA site to determine safe disposal...really that’s what it says !  

    (Click on any of the images below to enlarge them.)

    The Phillips LED bulb ( 75W equivalent since no 100 W equivalents are for sale yet) are selling for $40 at Home Depot with an incredible “expected lifetime “ of 22.8 years. Well at least you don’t have to contact EPA to determine how to dispose of them.


    IFTLE has found several more articles indicating that our concerns were/are justified. For example Bill Schweber’s guest commentary in EE Times,  “CFLs and their issues" [1/10/2012] . “My concerns are with the lies that have been told to Congress and the public regarding lifetimes of the new technologies (CFL and especially LED), and the significant increase in toxic materials associated with the disposal of these short-lived cheaply made devices.”

    "Although the lifetime of the LED devices may be rated at 40,000 to 100,000 hours at an appropriate temperature, just like we have all experienced with CFLs, the actual life of the device is generally much shorter due to higher temperature of operation of the device and due to the non-LED components in the assembly. After disassembly of several failed CFL devices and some LED devices, we as a community should understand that the cheap manufacture of such devices will lead to serious pushback and disillusionment of our customers.”

    "The use of aluminum capacitors in CFL and LED Edison-base devices should be avoided at all costs, and yet it seems that every CFL and LED device I have disassembled, and the photos of every such device I have seen postings of disassembly for, use cheap aluminum capacitors with low temperature ratings. As consumers, most of us are aware that the CFL and LED Edison-base devices fail rapidly in closed fixtures, in outdoor use, in refrigerators and oven use...LED power output are specified at 25° and unless properly heatsinked, the higher the temperature the less light output with aging and less service life, probably 70° max temp is acceptable, but many work above this limit, so life span is not what is publicized.”

    Giving credit where credit is due, IFTLE should note that the DOE takes a  good look at these issues in their second LED report “LED LUMINAIRE LIFETIME: Recommendations for Testing and Reporting” [June 2011].

    Quoting from this report : The statement “100,000 hours of LED luminaire lifetime” is gradually giving way to the realization that there is little consistency, very little published data, and few hard facts around so-called luminaire lifetime numbers...sometimes only lumen depreciation...of the LEDs is considered in estimating useful life of the luminaire product...a problem, since failure or degradation of drivers, optics, or other components can lead to  total failure. Like other parts of the lighting system, the devices and components used to convert line power to direct current suitable to drive and control LEDs affect lifetime and reliability. Capacitors, inductors, transformers, opto-isolators, and other electrical components all have different design lifetimes, are affected by operating and ambient temperature, and are vulnerable to electrical operating parameter variations from surges, spikes, and so forth. An effective LED system-reliability evaluation must take all of these aspects into consideration... Additional information that should be readily available to the purchaser, although not on the label itself, should include maximum ambient temperature of operation to achieve this depreciation performance, the number of hours actually tested on which the projection is based, and the type of projection...”

    These modifications to the initial DOE report were driven by articles such as  LED Driver Lifetime and Reliability hold thekey to success in LED Lighting Projects” by George Mao and Marshal Miles in the Sept/Oct 2010 issue of LED magazine.

    Mao and Miles contend that “the light engine of properly designed LED lighting systems should last for up to 50,000 hrs. However, unless the power electronics...are designed for the correspondingly long life and high reliability, this will not be realized”   

    Estimating the life of any product is primarily a matter of identifying all known wear out mechanisms and identifying the shortest lived component in the system that will render the product inoperable” Their choice for the component that would fail in the shortest time is the electrolytic capacitor. The temp that the fixture operates at appears to be a determining factor in the lifetime of such components.

    Another concern is the hype surrounding how much money will be saved. IFTLE found this nifty little calculator on the Consumers Power web page. [link]  

    What I have totaled up in the table below is pretty close to what power costs me in my NC home. Basically, for me , air conditioning is 75% of my power bill and even in the winter  Lester (incandescent bulbs) only account for 13 % of my power bill. 

    Since this comes pretty close to my summer and winter electric bills, it shows that cutting my lighting bill by ¾ would save me ~ 36$ a year ( 3$ per month) which would pay for  less than 1 LED bulb per year and take me 25 years to break even on bulb replacement  in my house. It also confirms, for me, that in the average household, replacement of all the bulbs in the house with LEDs would not be seen on your monthly power bill. Sorry but the $3 savings will be lost in the noise.
    On the country's overall energy bill you may be able to see the effect, but on the average consumers monthly power bill, after spending $1000 to replace all the bulbs with LEDs, you will not ! The public is clearly being deceived !
    Our friend Lester was set up, framed and is about to be executed for “the big energy lie” !
                                                      STOP the BS, SAVE LESTER the LIGHTBULB !


    For all the latest in 3DIC and advanced packaging stay linked to IFTLE...........

    IFTLE 97 DATE in Dresden, Synopsys 3D EDA Solution

    April 15, 2012 8:58 AM by Garrou
    This year's Design, Automation and Test Europe Conference [DATE] was held in Dresden.  This year's 1 day 3D Integration workshop was headed up by Sandeep K. Goel (TSMC), Qiang Xu (Univ Hong Kong) and  Saqib Khursheed (University of Southampton).


    ARM, IMEC and the Swiss Federal Institute of Technology (EPFL) gave an interesting presentation on the "Performance and Efficiency of 3D Stacked DRAM in a Multicore System." The goal of this 2010 - 2012 European commission funded project, known as "Euro Cloud," is to integrate ARM processor cores with 3D DRAM for very dense, low power data centers for mobile cloud services for hand held devices. Coupling of high performance ARM Cortex processors with 3D memory is  targeting the mobile cloud services from Nokia which will serve millions of "mobile handsets."  Their analysis shows that although 3D-stacked DRAM, such as Wide-IO, allow for wider buses by providing increased pin density, the wider buses saturate in providing additional throughput. The authors propose that rather than increasing the width, more channels that are effectively managed by memory controllers lead to increased overall system performance. They also conclude that 2.5D is preferable to 3D for systems with challenging thermal performance.

    (Click on any of the images below to enlarge them)

    Hsien-Hsin Lee of Georgia Tech presented more details on their 3D MAPS massively parallel processor with stacked memory [we have discussed this previously in IFTLE 93, "2.5 / 3D at the 2012 IEEE ISSCC"] 
    Of interest were their designs for V2 which will have 5 layers and a wide IO interface. It is shown schematically below with proposed specs compared to 3D MAPS 1

    The Fraunhofer ASSID group presented their thoughts on quality inspection strategies for 3D chip processes. Their concept is that I line metrology is needed to save time and materials.
    TSV metrology tasks include : determination of uniform TSV depth; barrier and seed defects and voids during TSV filling and  determination of bump height and coplanarity in copper pillar bump interconnect.

    Synopsis unveils its 3DIC EDA solution
    Synopsys recently  unveiled its comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products.
    Synopsys reports that they are  delivering a comprehensive EDA solution including :

    -DFTMAX: design-for-test for stacked die and TSV
    -DesignWare STAR Memory System: integrated memory test, diagnostic and repair solution
    -IC Compiler: place-and-route support, including TSV, microbump, silicon interposer redistribution layer (RDL) and signal routing, power mesh creation and interconnect checks
    -StarRC Ultra: parasitic extraction support for TSV, microbump, interposer RDL and signal routing metal


    -HSPICE and CustomSim circuit simulation: multi-die interconnect analysis
    -PrimeRail: IR-drop and EM analysis
    -IC Validator: DRC for microbumps and TSVs, LVS connectivity checking between stacked die
    -Galaxy Custom Designer: specialized custom edits to silicon interposer RDL, signal routing and power mesh
    -Sentaurus Interconnect: thermo-mechanical stress analysis to evaluate the impact of TSVs and microbumps used in multi-die stacks
    The Synopsys 3D-IC solution is expected to be in production in calendar Q2 of 2012.
    For all the latest in 3DIC and advanced packaging stay linked to IFTLE....................

    IFTLE 96 A New Concept for a 3DIC Conference; Granddaughter Update

    April 9, 2012 5:03 PM by Garrou
    In the past IFTLE has ranted about how every technical conference on the face of the planet wanting  a piece of the 3D integration pie and how that is propagating severe redundancy in the presentations that are being given.  Paying $500 + travel expenses for a conference that gives you 15 3D presentations when you have already seen 12 of them under slightly modified titles can be upsetting. Going to a conference that gives you 1 session of  3DIC presentations and you’ve seen all 5 of them is even worse.  I don’t blame the presenters,  because I know they are being begged by the session chairs to submit their presentations even if they admit that they have nothing new to say.

    Having said that, I must admit I was intrigued by the concept of the new conference “Connect in 3D” being sponsored by Yole Developpement this coming  fall ( Oct 31st / Nov 1st). For those of you who haven’t seen the advertising blurb try this link [link]
    The concept originated with Brian Perkins of Highliner Events (yes that would be Jeff Perkins brother – isn’t nepotism great).  While many conferences try to set up their schedule so that the attendees can have “quality networking time”  Brian’s concept is to  have a conference that is basically all networking complete with terms like “speed dating”.  Will it work for a technical area like ours ?

    IFTLE decided to throw some questions Brian and Jeff’s way so we can all get a better understanding about how this works.
    IFTLE: Brian How did this “connect” program come about ? Has it been used in other technical venues and if so how has it worked.
    BP: The real value of a conference is no longer the presentations, keynote addresses, or even white-papers. It is the decision-makers and influencers who attend—and the networking and collaboration  that occurs between them at the event—that are truly high-value. Networking is the Holy Grail of event value, and our Collaboration SummitsSM are designed to deliver the maximum networking opportunities in a variety of pre-scheduled, formal and informal formats with a minimum of ‘pre-packaged’ content. Yole has used the technique for a MEMS event, I’ll let Jeff address how he felt that went.
     ï»¿ JP: We launched our first event with Highliner last year targeting the MEMS inertial sensor space. Attendees at  the inaugural “MEMS in Motion” event really embraced the format.  As a technical crowd, they “got it” very quickly, everyone used the software tools to the max and respected every meeting time limit – making the absolute most of their time.  Attendees gave us a 100% satisfaction rating. This event design is an iterative and evolving process. These second edition Collaboration Summits have been revised based on feedback and observations made during the first event. We will continue to respond to the market as it dictates.




    IFTLE: Will attendance be capped by total or by company ?
    JP: We would like to see no more than 200 participants. At sometime we might also consider capping the number of participants from a single company. The value proposition being more companies participating is better.
    IFTLE: If I have read the material correctly it looks like two types of meeting are set up. Some by the attendee and some by a computer which matches up attendees randomly. Is that correct? How does this work?

    BP:   The bulk of the meetings are scheduled by the attendees themselves.  Attendees request, accept and or decline meetings with other attendees.  These will be 20-minute meetings with delegates of their choice, scheduled through the DealCenter online platform or at kiosks during the event. Private tables are setup for conference attendees to meet with the person(s) they made appointments with through the DealCenter. Confirmed meetings will be assigned a table number in the Connect in 3D meeting area.  In addition, there is a session where there is “speed dating” pre-arranged meetings which we will talk about in a few minutes….
    JP: The DealCenter will open in September. Registered attendees will receive instructions in September via email when the DealCenter opens. All meeting planning is done through the DealCenter platform and every registered attendee will be able to see and request meetings with all other registered attendees. To be clear though - no contact information outside of the DealCenter contact point is ever made available unless users voluntarily provide it through their own meeting invitations or sent messages. So DealCenter is a temporary networking tool, setup for each event, allowing initial contact to be made, but any expansion of that contact is entirely up to you.
    IFTLE: So all the attendees will be listed and I can privately sign up for 1 on 1 meeting with any of them before I get to the meeting. Those meetings are locked in – correct ?
    BP: Remember the whole concept is about choice, so when I request a meeting with you, you have three options, you can accept the meeting, you can accept the meeting but suggest a different time, or you can decline the meeting. If you accept the meeting that is locked into our respective schedules.
    IFTLE: What are the chances that the person I really want to meet will get booked up and I wont get to talk to him/her ? 
    JP: It is entirely possible that the person you want to meet will be booked up for the 20-minute meetings, particularly if you wait until the last minute to register for the conference early bird registration really means something in this style event! However, all is not lost if they are booked - there is the possibility you will end up with a 10-minute speed dating meeting on the first day. Also there are all of the classic informal opportunities to meet: at the meals, we have extended coffee breaks and receptions. We actually enhance the ability to meet people by starting out the meeting with personal introductions. One of the key components to these events is the opening session introductions: so right after breakfast on the first day all of the participants gather in the plenary session room. We give a brief description of how the day will run, and then we begin the individual introductions.  It allows everyone to put a face with a name. If there is someone you really want to meet, you will know who they are and what they look like in the first 2 hours. You don’t have to wander around all day trying to read name badges.
     IFTLE: So how does the speed dating part work ?
    BP: One of the important parts of any gathering of business professionals is the random connections that occur by serendipity. Our Meet the Market ( speed dating) meetings are designed to enhance that serendipity. These meetings will be set by the DealCenter program software a few days before the event. We want to be sure we have the maximum number of participants available to insure we capture everyone. The system will randomly pair attendees with other attendees screening for one meeting per individual from a given company and screening out anyone with whom you have already scheduled a 20-minute meeting.
    IFTLE: What if speed dating assigns me to meet with a competitor, do I have to have those meetings ?
    JP: The speed dating session is really about going with the flow.  We issue individual “date cards” minutes before the Meet the Market session starts and you go to each and every meeting, regardless of any sentiments you may have.  These meetings are 10 minutes – long enough to know if there is need to meet again, but not so long to make you uncomfortable.  At MEMS in Motion, even competitors that got paired up commented that they actually made a useful connection - serendipity indeed.   
     IFTLE: So what is the proportion of prepared materials (plenary presentations by experts / panel discussions) vs scheduled 20 min meetings vs speed dating over the two days ?
     BP : It breaks out to be just about 1/3 each  plus all the informal networking time at meals, breaks and receptions.  If you add in this informal time the breakdown is about 25% each
    IFTLE : So to sum up, this is a conference which focuses on relationship building  through 2 days of networking in Palm Springs where you can get to have direct 1:1 meetings with people you have been wanting to meet ?
    JP: In today’s world we are all too busy, the real point here is to make enough of a connection so that folks will pick up the phone when you call or open and reply to an email you send.
    Update on the Girls
    On the way to the IMAPS  Device Pkging Conf. stopped off in TX for the weekend to see how Hannah and Maddie  were doing. Ends up it was Rodeo weekend in Houston. Trust me you have never been to a rodeo till you’ve attended one in TX.  For those of you who do not understand why the Texas football team are known as the “longhorns” ... Now you do !

    For all the latest in 3DIC and advanced packaging stay linked to IFTLE....................

    IFTLE 95 3DIC ��? Time Flies When You're Having Fun; Further Details on the Micron HMC , Equipment Suppliers Continue Consolidation, EVG Temp Adhesive Open Platform

    April 1, 2012 9:59 AM by Garrou
    Time Flies When You're Having Fun with 3DIC

    Seems like yesterday that the packaging world was hearing that Fujitsu, Toshiba, NEC, Oki, Renesas and others had formed a pre-competative consortium under the Association of Super Advanced Electronics Technologies  to study direct connecting of chips with through silicon vias (TSV). It seems like yesterday but it was 1999, 13 years ago.  
    In Feb 2005 my first article on the topic “Future IC’s Going Vertical” was published in Semiconductor International predicting that the industry would eventually have to move in this direction. A short month later, March 2005 I felt like a prophet when a TSV based 3D stacking approach was described by Intel’s Justin Rattner (todays CTO) at the Spring Developer Forum, with statements like “...stacked wafers and stacked dies using thru-silicon vias are showing promise in meeting the memory bandwidth challenge.”

    A year later, in April 2006 headlines from Soeul read “... Samsung has developed a new "3D" package, which reduces space requirements and increases performance capabilities of today's multi-chip packages. The company plans to use the technology to improve its NAND Flash packaging starting in 2007” Samsung announced that its new wafer-level processed stack package (WSP) rather than using wire-bonding .... micron-sized holes that penetrate through the silicon vertically to connect circuits directly - TSV. According to Samsung the technology would enable manufacturers of mobile and consumer electronics devices to achieve better electrical performance and design slimmer and high-performance handset designs that provide improved battery time. The announced that the technology would enter mass production in 2007, for NAND Flash packages initially. And that they planned to use WSP for server DRAM stack packages sometime down the road.

    A year later, in April of 2007, the headlines were “ IBM has announced that they're relatively close to going commercial with a "through silicon via" (TSV) technology that will enable them to create high-bandwidth connections between two or more chips in a stacked packaging format." The big news about IBM's design is that the company intends to start shipping product samples based on this technology in the second half of this year, with full production coming in 2008. "Looks as if TSV will be here faster than anyone previously thought."
    Now, thirteen years later ASET is in its 3rd incarnation “the Dream Chip program” , it is obvious that DRAM will be stacked before NAND flash hopefully in HVM by 2013 (not 2007) , IBM has announced a major memory program with Micron (though not in 2008) and we are still awaiting any word of commercialization from Intel. Certainly it’s fair to say that this is taking a bit longer than we all thought, even those of us who were trying to be ultra conservative.


    Micon / IBM  HMC – further details

    IFTLE has been sent a few messages asking for further details on the Hybrid memory cube production.
    Micron has announced that they will be manufacturing the memory layers and have contracted with IBM to manufacture the logic layer. Micron will be doing the assembly of the layers at a yet to be disclosed location. For now we can assume they are doing the initial production in Boise. For our initial discussions on this technology see IFTLE 74, “The Micron Memory Cube consortium”.

    The technology described by M. G. Farooq of IBM last December at the IEEE IEDM [ see IFTLE 82 “3DIC at the 2011 IEDM...”] is the technology being used to create the logic layer in the HMC stack (blue layer).

    (Click on any of the pictures to enlarge them)


    As noted in IFTLE 82, TSVs are integrated at “fatwire” (upper level metal) levels to optimize wire-ability and process complexity with 4 to 12 metal levels including low-k interlevel dielectric (ILD). TSV of less than 100 µm depth were etched with near vertical sidewalls at a minimum pitch of 50 µm. An example of this is shown below. It is believed that the Micron logic layers  are being done in SOI technology.


    The logic layer for the HMC parts will be manufactured at IBM's advanced semiconductor fab in East Fishkill, N.Y., using the company's 32nm, high-K metal gate process technology [link]



    Chipworks has concluded that “ it appears that the TSVs are annular. Once the lower metal / dielectric stack is formed (including the via dielectric for the metal layer that contacts the TSVs), the TSVs are drilled through to the silicon, and then a Bosch etch is used to drill the vias about 100 µm into the substrate, with a minimum pitch of 50 µm. After drilling, a conformal oxide is deposited, the barrier and seed layers are sputtered in, the copper fill is plated in, and any excess copper is CMP’d off. The dielectric for the contact level metal is put down, and then the top fat-wire metal levels are conventionally defined.” [link]

    TEL acquires Nexx

    Tokyo Electron Limited (TEL) has acquired semiconductor packaging equipment supplier NEXX. Nexx advanced deposition equipment, including electrochemical deposition (ECD) and physical vapor deposition (PVD) tools will be added to the TEL line of products aimed at back end packaging applications and 3DIC.


    Long time readers know that this has been a theme identified by IFTLE [ see PFTLE 41, “ 3D Integration Stays Hot at Semicon West” or PFTLE 107 "3D News:Applied/Semitool, TSMC, Ziptronix”


    Looks a lot like the front end heavy weights Applied, LAM and TEL are going to buy up all the pieces they need to become the 3 heavyweights in packaging and 3D. Consolidation will continue because with fewer and fewer players moving to 22 nm and beyond packaging is a natural evolution for some of these big front end equipment vendors.



    Shin-Etsu Joins EVG Temp Adhesives open platform
    Shin-Etsu’s adhesives will be entering qualification trials on EVG’s EZR (Edge Zone Release) and EZD (Edge Zone Debond) modules, which support the new ZoneBOND room temperature debonding process. Shin-Etsu is the first participant to announce for the program since its inception late last fall [ see IFTLE 76, “ Adv Pkging at IMAPS 2011: recent 3D Announcements”.
    EVG’s ZoneBOND temporary bond / debond  solutions and open materials platform include:  the use of silicon, glass and other carriers; compatibility with existing, field-proven adhesive platforms; and the ability to debond at room temperature with virtually no vertical force being applied to the device wafer.  To support grinding and backside processing at high temperatures and to allow for low-force carrier separation, the concept defines two distinctive zones on the carrier wafer surface with strong adhesion in the perimeter (edge zone) and minimal adhesion in the center zone.  For further description of the technology see IFTLE 90 "Highlights from the IEEE 3DIC 2012 Japan" and refs therein.  
    For all the latest on 3DIC and advanced packaging stay linked to IFTLE..................

    IFTLE 95 3DIC – Time Flies When You're Having Fun; Further Details on the Micron HMC , Equipment Suppliers Continue Consolidation, EVG Temp Adhesive Open Platform

    April 1, 2012 9:59 AM by Garrou
    Time Flies When You're Having Fun with 3DIC

    Seems like yesterday that the packaging world was hearing that Fujitsu, Toshiba, NEC, Oki, Renesas and others had formed a pre-competative consortium under the Association of Super Advanced Electronics Technologies  to study direct connecting of chips with through silicon vias (TSV). It seems like yesterday but it was 1999, 13 years ago.  
    In Feb 2005 my first article on the topic “Future IC’s Going Vertical” was published in Semiconductor International predicting that the industry would eventually have to move in this direction. A short month later, March 2005 I felt like a prophet when a TSV based 3D stacking approach was described by Intel’s Justin Rattner (todays CTO) at the Spring Developer Forum, with statements like “...stacked wafers and stacked dies using thru-silicon vias are showing promise in meeting the memory bandwidth challenge.”

    A year later, in April 2006 headlines from Soeul read “... Samsung has developed a new "3D" package, which reduces space requirements and increases performance capabilities of today's multi-chip packages. The company plans to use the technology to improve its NAND Flash packaging starting in 2007Samsung announced that its new wafer-level processed stack package (WSP) rather than using wire-bonding .... micron-sized holes that penetrate through the silicon vertically to connect circuits directly - TSV. According to Samsung the technology would enable manufacturers of mobile and consumer electronics devices to achieve better electrical performance and design slimmer and high-performance handset designs that provide improved battery time. The announced that the technology would enter mass production in 2007, for NAND Flash packages initially. And that they planned to use WSP for server DRAM stack packages sometime down the road.

    A year later, in April of 2007, the headlines were “ IBM has announced that they're relatively close to going commercial with a "through silicon via" (TSV) technology that will enable them to create high-bandwidth connections between two or more chips in a stacked packaging format." The big news about IBM's design is that the company intends to start shipping product samples based on this technology in the second half of this year, with full production coming in 2008. "Looks as if TSV will be here faster than anyone previously thought."
    Now, thirteen years later ASET is in its 3rd incarnation “the Dream Chip program” , it is obvious that DRAM will be stacked before NAND flash hopefully in HVM by 2013 (not 2007) , IBM has announced a major memory program with Micron (though not in 2008) and we are still awaiting any word of commercialization from Intel. Certainly it’s fair to say that this is taking a bit longer than we all thought, even those of us who were trying to be ultra conservative.


    Micon / IBM  HMC – further details

    IFTLE has been sent a few messages asking for further details on the Hybrid memory cube production.
    Micron has announced that they will be manufacturing the memory layers and have contracted with IBM to manufacture the logic layer. Micron will be doing the assembly of the layers at a yet to be disclosed location. For now we can assume they are doing the initial production in Boise. For our initial discussions on this technology see IFTLE 74, “The Micron Memory Cube consortium”.

    The technology described by M. G. Farooq of IBM last December at the IEEE IEDM [ see IFTLE 82 “3DIC at the 2011 IEDM...”] is the technology being used to create the logic layer in the HMC stack (blue layer).

    (Click on any of the pictures to enlarge them)


    As noted in IFTLE 82, TSVs are integrated at “fatwire” (upper level metal) levels to optimize wire-ability and process complexity with 4 to 12 metal levels including low-k interlevel dielectric (ILD). TSV of less than 100 µm depth were etched with near vertical sidewalls at a minimum pitch of 50 µm. An example of this is shown below. It is believed that the Micron logic layers  are being done in SOI technology.


    The logic layer for the HMC parts will be manufactured at IBM's advanced semiconductor fab in East Fishkill, N.Y., using the company's 32nm, high-K metal gate process technology [link]



    Chipworks has concluded that “ it appears that the TSVs are annular. Once the lower metal / dielectric stack is formed (including the via dielectric for the metal layer that contacts the TSVs), the TSVs are drilled through to the silicon, and then a Bosch etch is used to drill the vias about 100 µm into the substrate, with a minimum pitch of 50 µm. After drilling, a conformal oxide is deposited, the barrier and seed layers are sputtered in, the copper fill is plated in, and any excess copper is CMP’d off. The dielectric for the contact level metal is put down, and then the top fat-wire metal levels are conventionally defined.” [link]

    TEL acquires Nexx

    Tokyo Electron Limited (TEL) has acquired semiconductor packaging equipment supplier NEXX. Nexx advanced deposition equipment, including electrochemical deposition (ECD) and physical vapor deposition (PVD) tools will be added to the TEL line of products aimed at back end packaging applications and 3DIC.


    Long time readers know that this has been a theme identified by IFTLE [ see PFTLE 41, “ 3D Integration Stays Hot at Semicon West” or PFTLE 107 "3D News:Applied/Semitool, TSMC, Ziptronix”


    Looks a lot like the front end heavy weights Applied, LAM and TEL are going to buy up all the pieces they need to become the 3 heavyweights in packaging and 3D. Consolidation will continue because with fewer and fewer players moving to 22 nm and beyond packaging is a natural evolution for some of these big front end equipment vendors.



    Shin-Etsu Joins EVG Temp Adhesives open platform
    Shin-Etsu’s adhesives will be entering qualification trials on EVG’s EZR (Edge Zone Release) and EZD (Edge Zone Debond) modules, which support the new ZoneBOND room temperature debonding process. Shin-Etsu is the first participant to announce for the program since its inception late last fall [ see IFTLE 76, “ Adv Pkging at IMAPS 2011: recent 3D Announcements”.
    EVG’s ZoneBOND temporary bond / debond  solutions and open materials platform include:  the use of silicon, glass and other carriers; compatibility with existing, field-proven adhesive platforms; and the ability to debond at room temperature with virtually no vertical force being applied to the device wafer.  To support grinding and backside processing at high temperatures and to allow for low-force carrier separation, the concept defines two distinctive zones on the carrier wafer surface with strong adhesion in the perimeter (edge zone) and minimal adhesion in the center zone.  For further description of the technology see IFTLE 90 "Highlights from the IEEE 3DIC 2012 Japan" and refs therein.  
    For all the latest on 3DIC and advanced packaging stay linked to IFTLE..................

    Experts Discuss Interposer Infrastrucrure at IMAPS Conference

    March 24, 2012 10:27 AM by Garrou
    IFTLE brought together a  panel of manufacturers, users and market specialists at the 2012 IMAPS Device Packaging Conference in Fort McDowell AZ to discuss the Evolving 2.5D / 3D Infrastructure. [ Douglas Yu, Sr Director of front end and back end technology development for TSMC; Jonathon Greenwood, Director of Packaging R and D at GlobalFoundries;  Remi Yu, Deputy Division Director of UMC]memory suppliers [Nick Kim, VP of future electronic packaging technologies at Hynix] assembly houses [ Rich Rice, Sr VP of sales for ASE and Ron Huemoeller, VP of Advanced 3D interconnect at Amkor] users [Matt Nowak, Sr Director of Engineering at Qualcomm] and Market specialists [ Jan Vardaman, President of TechSearch Inc].

    (Click on any of the images below to enlarge them)

           [l to r] Doug Yu [TSMC], Garrou [IFTLE],Huemoeller [Amkor], Vardaman [TechSearch],
    Greenwood [GlobalFoundries], Yu [UMC], Kim [Hynix], Nowak [Qualcomm], Rice [ASE]



    When asked whether 2.5/ 3D TSV technology has been narrowed down to copper TSV middle from IDM or foundries and some vias last backside all the panelists agreed with this conclusion. When asked about standard TSV dimensions, the foundry and OSAT representatives all agreed that 5-8 µm  on 50 µm thick Si looks like it has become the standardized offering that many of their customers are expressing interest in. When it came to interposers, they similarly all gave the nod to 100 µm thick interposers with ~ 10 um diameter TSV. 
    Sourcing Interposers
    A significant portion of the panels time was spent discussing current and future interposer sourcing. Assuming the attributes of “fine”vs “coarse” interposers as defined in the table below, the question becomes “where will these interposers be coming from” and “what will they be used for” ? 

    So far announcements from Xilinx and Semtech indicate that they will both be using “fine pitch” interposers i.e fabricated by ~65 nm dual damascene [DD] CMOS processing by TSMC and IBM respectively. Altera and Nvida have also announced similar high density interposers for future use as have other graphics chip makers.
    While all the OSATs have RDL technology capable of fabricating “coarse” interposers so far none of the major players [ ASE, Amkor, SCP, SPIL] have announced that they are entering the interposer business.

    While all of the current roadmaps point to 2012-2014 as being the date for initiation of mass production for 2.5/3D products one must now ask where is the interposer production to meet this demand. If these lines are not in place now, is it easonable to think that products using them be qualified and in mass production within the next 24 months ?
    During his conference presentation Amkors Huemoeller indicated that they would not be manufacturing interposers and their search of the industry for sources  indicated that only 3 players were close to being ready to deliver interposers that wee useful to Amkor, namely TSMC, UMC and GlobalFoundries.
     While glass panels and even possibly advanced laminates presented interesting possibilities for low cost future products, Amkor’s perspective is that  they are in the earliest stages of R&D.
    All 3 of the foundry panelists indicated that they will be commercializing fine featured interposers although as we stated only TSMC and IBM had announced small volume product production has been initiated.
    When asked about rumors circulating that OSATS are looking to put equipment in place to manufacture DD “fine pitch“ interposers, both Amkor and ASE indicated that they had no plans to do so.
    IFTLE concludes that despite significant “industry chatter” the only programs that can afford interposers, so far, are programs that require the density or other attributes provided by fine featured interposers which can only be provided today by foundries /3D active IDMs. While we can anticipate that there might be products in the future that can be designed to take advantage of “coarse” interposers, and some of the initial fine interposer activities such as memory + logic + graphics chip applications might be able to migrate to coarse interposers as they become available, we will, initially at least, be limited by the availability and cost of foundry supplied interposers. 
    The Evolving Infrastructure
    TSMC reconfirmed  that they will provide full 2.5 / 3D service including chip design and fabrication, stacking and packaging [ see “2.5D announcements at the Global Interposer Techconferenceand “TSMC repeats call for foundry-centric 2.5/3D industry” ]
    TSMCs Yu indicated that they have made their thoughts clear in the past few months and it can be found clearly delineated on their web page. During his plenary lecture Yu once again indicated that fabrication of chips on interposers was not as easy as making prototypes makes it look and they strongly favored controlling and being responsible for the full process.
    When asked about supplying memory needs, Yu indicated that they would also handle that by having partnerships in place to supply the required memory although these partners were not identified.
    When asked for their positions, UMC and Global Foundries indicated a preference to work under the open ecosystem model where chips from various vendors could be stacked and assembled by OSAT partners.
    When asked how the current economic issues surrounding Elpida was affecting the UMC/Elpida/PTI partnership, UMCs Remi Yu responded that this was only one engagement that they had in place for 2.5/3D and that they were moving forward with others.
    Amkor’s Huemoeller indicated that foundries would be supplying interposers and they [ the OSATS] would be assembling them.
     ASE agreed short term but indicated that longer term they envisioned a broad “pie” with space for several types of players. ASE envisions future applications where coarse interposers would find their niche and be an important part of the technology base
    Both of the OSATS, as would be expected, favored the open ecosystem model where chips from various suppliers would be assembled at the OSATS. 
    Qualcomm reiterated a position that they have expressed in the past which is that interposers would add substantial cost to 3D stacking and as such probably would not be a broadly accepted solution for low cost mobile products
    TSMCs Yu responded that indeed the addition of an interposer added cost to  the overall component, but that “...this [2.5D] solution also offers cost savings by reuse of IP and separating digital and analog circuitry and allowing partitioning of costly SoC “ and that this in fact could make it the lowest cost solution..
    When Hynix was asked whether they would be offering memory stacks containing TSV as have been already announced by Samsung, Micron and Elpida Hynix Kim responded that he expects “2 and 4 chip memory stacks with TSV to be in mass production in 2013”
    When the panel was asked with the wide IO memory standard is now in place. what other standards were needed quickly Nowak of Qualcomm indicated that the upcoming Semi handling and transport standards were needed and noted that standardization was also needed in the ESD area and  standardization in the “design exchange formats” where he feels Si2 is taking the lead.
    When asked for their opinion on the current status of design tools all 3 of the foundries indicated that current design tools are adequate to move forward. Qualcomm’s Nowak offered that logic on logic design tools were still lacking.
    In terms of test strategies UMC would like to see some better standardization in the test area while Yu of TSMC drew a chuckle from the crowd when he noted that test needed to be minimized. Similarly, on the assembly front Rice indicated that ASE is having to test “everything” till the yields are up and Amkor quickly concurred.
    Focusing on the first generation of 2.5/3D  stacking interconnect all accepted that this will be done with Cu/Sn eutectic by reflow or thermo-compression bonding.   When asked what was limiting direct Cu-Cu bonding all agreed that copper bonding was not ready for prime time just yet. Yu a strong proponent of copper interconnect, noted that current copper bonding options have yield issues that have not yet been overcome “current requirements for pads are too large and the required CMP of the interfaces is causing dishing that must be handled...HVM of copper –copper bonding options is tougher than showing research samples”
    When similarly asked about  hybrid metal/oxide bonding schemes where oxide / copper surfaces are polished flat, oxide bonded then subsequently oven annealed to strengthen oxide bond and form Cu-Cu bonds (as shown by Ziptronix and Leti) no panel members were willing to say that this technology was close to commercialization.  TSMC responded that these technologies required very flat surfaces which were difficult to obtain due to dishing and other issues and that in general such technologies were “not ready right now”.  ASE expanded that this option was not required to solve todays problems and therefore was being looked at as a interesting R and D solution which could find its niche later. During Q and A Cook of Ziptronix offered that she thought their technology was ready and simply awaiting the commitment of a significant player. When the panel questioned copper migration issues due to miss alignment of the Cu-Cu bonds, Cook offered that their process which encapsulates the copper pillars in nitride barrier. 
    Rumors abound that TSMC is designing the apple A6 processor for ipad and iphone with 3D TSV. When asked to comment on this or whether Samsung was also offering TSV in their design of the A6 this question brought the expected “no comment” from TSMCs Yu and silence from the rest of the panel. Similarly no one would offer up comment about who would be supplying Sony who announced that they would require TSV interposers for their next Playstation upgrade.
    When asked about timing for the expected HVM of wide IO memory stacks for tablets, Qualcomm responded probably 2013 and Hynix responded maybe 2015.

    For all the latest in 3DIC and advanced packaging stay linked to IFTLE................

    IFTLE 93 2.5 / 3D at the 2012 IEEE ISSCC

    March 17, 2012 4:50 PM by Garrou
    There were several interesting 2.5 / 3D presentations at the recent IEEE ISSCC conference.

    2.5D Integrated Voltage Regulator Using Magnetic Core Inductors on Silicon Interposer
    Minimizing energy consumption is a performance goal of all of today’s devices including  microprocessors. Dynamic voltage and frequency scaling (DVFS) is a technique for performing “on-the-fly” energy-use optimization. Implementation of DVFS requires voltage regulators that can provide independent power supplies and can transition power supply levels on nanosecond timescales, which is not possible with modern board-level voltage regulator modules (VRMs).

    Switched-inductor integrated voltage regulators (IVRs) can enable effective implementation of DVFS, but the primary obstacle facing development of IVRs is integration of power inductors. This work by Columbia University and IBM presents “an early prototype switched-inductor IVR using 2.5D chip stacking for inductor integration” by  combining magnetic materials, chip-stacking design and a 2.5D chip packaging process. The power converters integrated onto the same chip, or into the same package, as microprocessors "significantly improves computational performance per watt of power consumed

    They report that the technology can reduce power consumption, by 10-20% in a typical US data center
    Inductors are fabricated on the silicon interposer in an elongated spiral with a Ni-Fe magnetic core encasing the copper windings on the long axis.  “The Ni-Fe is deposited under a magnetic biasing field so that the hard axis of magnetization forms along the width of the core as shown in the figure. Inverse coupling between adjacent inductors, is utilized to avoid magnetic saturation of the core.” The inductor fabrication involves successive electroplating deposition of the bottom magnetic core, copper windings, and top magnetic core. The windings are electrically isolated from the bottom magnetic core with a layer of silicon nitride, and from the top core with ”hard baked photoresist”.

    (Click on any of the images below to enlarge them.)



    IBM Stacked Memory on Processor
    There have been rumors out there that IBM would be applying with their 3D technology in their upcoming Power7 devices. Their presentation at ISSCC may be the first look that we are getting at their early designs for processors stacked with cache memory using TSV technology.

    This work describes a prototype 3D system, constructed by stacking a eDRAM memory layer and logic blocks from the IBM Power7TM processor L3 cache, and a “processor proxy” layer in 45nm CMOS technology enhanced to include TSVs. The 3D stack is constructed using 50 µm pitch C4’s joining the front side of the thick processor chip to TSV connections on the back side of a thinned memory. The TSVs are Cu-filled vias that are ~20µm dia and <100 µm deep.
    Standard design methodologies with some 3D extensions were used to design each stratum. TSV locations for power and clock were pre-defined to match a regular grid. Some sites were de-populated to accommodate the eDRAM blocks.




    Tezzaron Technology Used for 2 Processors

    Old friend Bob Patti at Tezzaron was involved helping fabricate two of the processor modules shown at this years ISSCC

    Georgia Techs  3D-MAPS: 3D massively parallel processor with stacked memory
    3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5 x 5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density


    Tezzaron 3D technology was used to stack two logic dies using face-to-face (F2F) bonding, where the top die is thinned to 12µm and the bottom die is 765µm thick.  These F2F pads are used for signal and P/G connections between the two dies. The diameter of a F2F bonding pad is 3.4µm, and their pitch is 5µm. 3D-MAPS uses 235 I/O cells that are placed along the periphery of the core die. Each I/O cell contains 204 redundant TSVs, where each TSV connects between a metal 1 landing pad and a backside metal landing pad deposited on the backside of the silicon substrate. Each backside metal landing pad (56 x 56µm2) is wire bonded to the packaging substrate. The diameter, height, and pitch of a TSV are 1.2µm, 6µm, and 5µm, respectively

    University of Michigan Centip3De

    David Fick of the University of Michigan showed Centip3De another processor fabbed by Tezzaron. A 3-D IC stack using 128 ARM Cortex M3 cores and 256 Mbytes of stacked DRAM operating at near threshold voltage. The module has an un-thinned cache layer and a thinned core layer with WB connecting to TSV on the backside.


    Hynix Dealing with Process Variation in a 3D Memory Stack
    In general, commercial DRAM shows large process variation from chip to chip, which causes address access time variation (tAC).  In order to reduce the tAC variation, most high speed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption.   
    Hynix in their paper entitled “A 283.2µW 800Mb/s/pin DLL-Based Data Self-Aligner for Through-Silicon Via (TSV) Interface explains that this can be an even larger problem for stacked memory die. “For TSV-based stacked dies, large tAC variation results in higher power consumption due to short circuit current from data conflicts among shared IOs”. Since the number of IO  might be 512 or more for wide IO DRAM,  the additional power consumption can be very high. While it is desirable in mobile DRAM to exclude the DLL because of the power cost , TSV stacked DRAM for high-speed operation partially adopts a DLL in the master die (driver circuitry) . The DLL-based data self-aligner (DBDA) described by Hynix  reportedly reduces the data conflict time among stacked dies, consuming 283.2µW during read operation at 800Mb/s/pin. It dissipates 4.98µW in self-refresh mode with the help of leakage-current-reduction controller.

    For all the latest in 3DIC and advanced packaging stay linked to IFTLE..............

    InterNepcon, Loss of a Dear Friend

    March 10, 2012 11:13 AM by Garrou
    At the recent InterNepcon Japan Exposition held at the Tokyo "big site" their "IC Packaging Technology Expo" contained some new information and some retreads that we have seen on IFTLE previously. Below I'll cover a few new items that may be of interest to you.

    TI's Mark Gerber, a key player in bringing up their Cu pillar technology at Amkor addressed 3D packaging technology for next generation devices. Mark broke out current FC interconnect technologies into the following 4 categories indicating that fine pitch gold stud bumping was confined mainly to Japan.

    (Click on any of the images below to enlarge them)



    Sung-Il Cho of Samsung's test and package center looked at Samsung's Packaging Roadmap. He offered the following categorization for their DRAM, Flash and system LSI chips...



    ...and the following roadmap for flash technology development for solid state drives. Consistent with their corporate policy of holding new technology information "close to the vest" their inputs on 3D packaging with TSV were either ITRS roadmap slides or Yole roadmaps that have been published on these IFTLE pages before.



    Keiichirou Kata of Renesas Advanced Package Development Dept. addresses their packaging roadmaps. He sees the major developing areas as FC BGAs, WLP and what he calls 3D Jisso (3D IC integration). Their FC technology roadmap is driven by desire for tighter pitches.



    28 nm node chips will see a move to 108 um pitch and copper pillar bumps by the end of 2012.



    Their proposed fan out WLP is an RDL first technology which they contend eliminates the issues of chip movement due to mold compound shrinkage.




    They are moving to wide IO DRAM standards for low power DDR3 and beyond.



    Ryoji Matsushima from Toshiba's Memory Packaging Engineering Dept. discussed equipment materials and processing issues for thin memory packages. High memory capacity, high memory access speed and thinner packages all point towards memory stacking with TSV.



    Technical issues with thin packages are shown on the slide below.



    In Memorium: Jackki Morris Joyner



    This past week I was attending the IMAPS Device Packaging Conference in Ft McDowell AZ (coverage coming in a few weeks). Those of you who are long time readers of IFTLE know I am there every year and strongly support this IMAPS conference. In the end, what separates societies is people not content. Part of what makes IMAPS great to work with has been Jackki Morris, or as we knew her post marriage Jackie Morris Joyner. When she first told us of the impending marriage and that she was becoming Jackki Joyner we all teased her asking her to run around the buildng for us ( for our non US friends this is the name of a famous US Olympic runner) and she laughed along with us. Jackki was the kind of person who made your life better for having talked to her on the phone or corresponded by email. Everyone asks "how's it going" but she meant it. She genuinely cared about people... you just could tell.

    The last time I talked with Jackki she was working the IMAPS table with her husband Cliff Monday night. When she saw me she gave me a hug and she turned on her computer and showed me pictures I had sent her of my grandaughters a few years ago. She had pages and pages of pictures of all the friends she had made through IMAPS because she just was that way. We shared funny stories of past conferences and laughed before I let her get back to work.

    The next morning she was noticeably missing and Exec Dir Michael O'Donoghue revealed to several of us that Jackki had become quite ill during the night. By the time she made the hospital her heart had stopped several times and she was in intensive care with Cliff by her side. This cast a pall over the rest of the meeting and she remained in intensive are as we all left the meeting to go home. By the time I arrived home Friday she had passed away. The world is truly worse off today because this caring, loving person is gone.

    Our prayers are with Cliff and her family

    Anybody here seen my old friend Jackki
    Can you tell me where she's gone
    She cared and shared with a lot of people
    But it seems the good they die young
    I just turned around and she's gone

    IFTLE 91 IEEE 3DIC Japan 2012 part 2

    March 4, 2012 10:04 AM by Garrou
    Continuing to examine presentations from the 3rd Int IEEE 3DIC Conf held in Japan in Feb 2012.

    Copper Protrusion

    In the last several years PFTLE and IFTLE have brought copper protrusion to the forefront as an issue [see "Researchers Strive for Copper TSV Reliability" Semi Int, 12/03/2009] and reported on technical solutions as they appeared from IMEC [see IFTLE 6 "Cu-Cu and IMC Bonding Studies at 2010 ECTC..."]; TSMC [see IFTLE 34, "3DIC at the 2010 IEDM"] and others. IME has now reported on their study of 5 um x 50 um Cu TSV as they were annealed from 250 to 450C.

    Cu expands vertically because it is constrained by the surrounding silicon substrate. Because it expands plastically it does not return to its original length when the sample is cooled down.

    (Click on any of the images below to view the full-size version)



    The effects of anneal temp, anneal time, via diameter and via depth are shown below where "room temp" refers to the protrusion present after anneal and return to room temperature and high temp refers to protrusion after anneal while still at the elevated temperature. As with previous studies they found that CMP after anneal retards any further protrusion if the temperature is again elevated.



    Bottom line is that protrusion is minimized by small diameter, low aspect ratio TSV.

    Samsung System LSI Division has also looked at the Cu protrusion issue and report similar results i.e that Cu protrusion can be reduced by heat treatment before CMP and that Cu protrusion and delamination strongly depend on TSV dimensions.

    When the via diameter was in zone A all the vias showed high Cu extrusion and via delamination, but TSV diameters from zone B showed no problems.


    Micro-cracking caused by Lateral Extrusion

    Conference Chair Koyanagi and co-workers at Tohoku Univ also examined TSV dimensions and the effect of high temp annealing. An array of Cu TSV with diameters ranging from 3 to 30 um at three different pitches were annealed from 200 to 400C. Both the lateral and vertical protrusion of the copper was monitored.

    Again larger diameter TSV (at a constant depth) show higher extrusion, but also that lateral extrusion (extrusion in the x-y after Cu has protruded from the surface) increased with anneal temp. For example 5 um TSV on a 10 um pitch extrude laterally 2 um at 400C. This would put them within 1 um of touching! Stresses induced by the TSV also result in microcracking "...on the periphery of the TSV array and in between the TSV." Careful choice of TSV size and pitch is recommended.



    Cu-Cu Direct Bonding

    Copper-copper direct bonding continues to be a popular topic due to the promise of fine pitch, low resistance interconnect which are more mechanically reliable than IMC bonding (Cu-Sn-Cu) and should show less electromigration issues. Such processes are currently limited by the required bonding time / temperature which are usually reported as 30 min / 350-400C. The holy grail appears to be a thin die Cu-Cu thermo compression bonding process which requires low bonding temp and pressure.

    IMEC and TSMC have studied the direct Cu-Cu bonding of 5 x 40 um TSV with (3) different configurations ; (1) no nail head exposed (Cu CMP'd flat with the oxide surface; (2) flat nail head (cu CMP'd flat and then oxide recessed and (3) natural nail head (stop grind short of the nail head, pull back oxide revealing "dome" shaped copper protrusion. The matching landing pad is a Cu surface CMP'd flat with the oxide surface. After bonding they observed that the "no nail head exposed" and the "flat nail head" sample s delaminated even when the bonding temp and or the pressure was increased. They assumed failure was due to the low % area that is actually used to bond (less than 1%). So, what is good for the design (less than 1% of the area occupied by TSV) is not good for the strength of bonding. The dome bonding was better due to its ability to deform. IFTLE interprets this as an ability of the domed structured to deform allowing shorter TSV to now touch their pads and bond. IFTLE also thinks this is a good reason to look at hybrid bonding schemes such as proposed by Ziptronix [see PFTLE 48, "Opening the Kimono, Ziptronix gives details on DBI Process"] and CEA Leti [see PFTLE 103, "Show me the Copper"]

    Stacking of Ultrathin Die

    Standard 3DIC thickness has focused around 50 um for the last few years. IMEC has now shared their results of ultrathin (25 um) die stacking.

    After temporary bonding and grinding, oxide is pulled back for Cu TSV reveal. The revealed "nail heads" are passivated with 3 um BCB and reconfigured with Cu/BCB RDL. Cu/Sn bumps are then fabricated on the landing pads. The 25um thick die are diced while still bonded to the carrier. They note that "this is required to have enough mechanical support during stacking"

    Both NUF and WUF were looked at for underfill solutions. NUF is unfilled polymer dispensed onto the landing die prior to bonding and WUF is filled underfill film laminated to the thinned wafer while still on the carrier.



    Issues with NUF were: (1) underfill trapped between the bumps;(2) voids between top and bottom die and (3) induced topography due to underfill shrinkage on cure. Shrinkage of the underfill upon curing and the CTE difference between a microbump and the underfill cause a bending of the die over the ubump connection. For an unfilled underfill and a 25um thick die a 40% increase in the drain current was observed to occur.

    After several failed tries, they decided to focus on WUF with 60% filler loading. WUF was vacuum laminated onto the die and gave much better topography and the use of a filled underfill resulted in reduced stress.

    They also found that increase in the die thickness from 25 to 50 um resulted in a stress reduction of 3X. Final conclusions were that 50 um thickness die were currently much better option for scalable manufacturable process and that reduction in the TSV diameter from 5 to 3 um will reduce the required KOZ by 64%.

    Wireless Product with Design Partitioning

    ST Micro and CEA Leti described their program to partition the digital and analog functions of a HD video transmitter onto separate die and stack them using Cu TSV and ubumps.



    TSV are 10 um with a 40 um pitch and wafers are 80 um thick. Cu pillar interconnect are 25 um dia and 30 um high. Reliability tests were done at package level using JEDEC level 3. No delamination and no electrical failures were obtained after 1000 cycles.

    --------------The next IEEE 3DIC Conference will be held in the fall of 2013 in San Francisco--------------

    Coming up in IFTLE :
    -advanced packaging from InterNepcon Japan
    -3D as the ISSCC
    -detailed coverage on the IMAPS Device Packaging Conference and more

    For all the latest in 3D IC and advanced packaging stay linked to IFTLE............................

    IFTLE 90 Highlights from the IEEE 3DIC 2012 Japan

    February 25, 2012 9:27 AM by Garrou
    The 2011 IEEE 3DIC Conference scheduled for Japan, as most of you know, was postponed due to the earthquake and Tsunami issues Japan experienced last year. The good news is that the conference which was postponed till Feb 2012 was held a few weeks ago and was a huge success. More than 250 attendees shared 32 presentations and more than 65 posters concerning the latest breakthroughs in 3D stacking technology.

    In the next two blogs we will review what IFTLE considers some of the more important presentations and posters.

    Effect of Sidewall Roughness on Leakage Current

    Fujitsu has looked at the effect of sidewall roughness on leakage current comparing Bosch etched TSV to ULVAC NLD etched TSV (discussed below). Bosch etched scallops were 72 nm deep and 280 nm long while the NLD etched TSV were ultra smooth. 500 nm of SiON insulator was deposited by low temp PECVD (150C) followed by PVD of 50 nm of TiN and 50 nm of TI to serve as Cu barriers followed by 200 nm of Cu seed.


    Leakage current between TSV was measured after annealing for 5 min at from 200 to 400C. Leakage current of NLD is lower than the bosch etched TSV initially and is less than 100x smaller than Bosch after anneal at 400C. These results are correlated with cracking of the insulation layer and subsequent migration of copper. It appears as though sidewall roughness initiates crack growth. Since anneal at 400+ is recommended to reduce the effects of copper protrusion [see IFTLE 6 "Cu-Cu and IMC Bonding Studies at 2010 ECTC..."], it is recommended by IFTLE that such leakage current experiments be run when optimizing Cu anneal process during TSV fabrication to insure integrity of the barrier and insulation layers after processing.

    (Click on any of the images below to enlarge them.)
    Effect of Sidewall Roughness on Copper migration

    Koyanagi and his co-workers examined the influence of copper contamination on device reliability and found that when Bosch scalloping is high, conformal deposition of the dielectric layer and barrier layer is difficult and increases the likelihood of Cu atom diffusion through the thinned barrier on the point of the scallop especially during the thermal temperatures reached during post process thermal anneal.

    They fabricated Si trenches with 5 um diameter and 10 um depth with sidewall scalloping of 30 and 200 nm. 100 nm thick oxide and Ta barriers of 10 or 100 nm where deposited by sputtering. This was followed by a 200 nm thick copper seed.



    Electrical results showed the 10 nm Ta barrier failed to resist Cu migraion for both the shallow and severe scallops.



    ULVAC non Bosch scallop free TSV

    The magnetic loop discharge plasma (NLD plasma) used by ULVAC can be used for silicon or oxide etching. The etch profile is controlled by the SF6/O2 ratio. Sidewall roughness of less than 15 nm is obtained.



    IMEC and Suss Demonstrate Integration of ZoneBond Process

    IMEC has demonstrated integration of the ZoneBond process on their Suss XBC300-LF temporary bond cluster and DB12T peel debonder. The Zone bond process has been described before [see IFTLE 61, "Suss 3D Workshop at Semicon West"]

    The bonding material is coated on the wafers in 19.2 +/- 0.4 um thickness. Scanning acoustic microscopy shows that the bonding to a silicon carrier is void free.



    After thinning and backside processing the bonded wafers are soaked for a few hours in the adhesive solvent and laminated onto a UV sensitive dicing tape. The carrier wafer is then "peeled" off the device wafer.



    The remaining glue is then removed while the device wafer is held on the film frame. Devices are diced subsequent to cleaning.

    For all the latest in 3DIC and advanced packaging stay linked to IFTLE...........................

    IFTLE 89 Advances in CMOS Image Sensing

    February 20, 2012 11:28 AM by Garrou
    It was 5 years ago in the the fall of 2007 when Toshiba first announced the commercialization of TSV in a CMOS image sensor (CIS) [see "PFTLE 12 Imaging Chips with TSV announced..."; PFTLE 16, "More TSV Commercial capacity on line"; PFTLE 24, "ST Micro announces more CMOS Image Sensor Packaging Capacity with TSV"; PFTLE 57 "Toshiba CIS Camera Module Details..."; etc]. The next step of circuit repartitioning and stacking was interrupted by "back side imaging" [BSI], which flipped the chip over and let the light enter through the least obstructed side to let more light in per pixel, which is really important as the pixels are getting smaller and smaller. [see PFTLE 40, "Backside Illumination next for Next Generation CMOS Image Sensors"; PFTLE 46, "on Mechanical Bulls, Rollercoasters and CIS with TSV."

    For those of you needing a refresher about how this is done, below is a process flow that Yole Developpment released in 2010 starting with SOI wafers.

    (Click on any of the images to enlarge them)

    From SOI to Bulk Silicon

    Last spring Chipworks announced that Sony had moved from an SOI based process to a bulk silicon process. [link] It is unclear yet whether this will become an industry wide trend.

    Chipworks found that while previous Sony BSI sensors they had analysed were fabricated using an SOI starting wafer, with the 1.1µm BSI generation, Sony migrated to using bulk silicon substrates instead of SOI. Chipworks commented that SOI is a more costly substrate, but likely an easier process to implement. They presume that Sony was able to identify the yield limiting contributions from the bulk polishing process, and fine tune the yield to achieve a high yielding and very cost effective process. This process would require a SiO2 bonding process.

    In late August Ziptronix announced that Sony had taken a license on Ziptronix's patents regarding oxide bonding technology for backside illumination imaging sensors [see IFTLE 65, "...Ziptronix Licensing News"]

    With BSI fully implemented, it appears that practitioners have now turned their sites back to repartitioning the circuitry and creating true stacked 3D IS structures.

    Sony reveals stacking in BSI CMOS Image Sensor

    In January Sony announced that it had developed "the next generation back-illuminated CMOS image sensors" by separating the pixel section containing the back-illuminated structure pixels from chips containing the circuit section for signal processing, which is in place of supporting substrates for conventional back-illuminated CMOS image sensors. [link] This results in:
    -More compact image sensor chip size
    -Higher image quality of the pixel section by optimizing the manufacturing processes for superior image quality on the pixel layer
    -Faster speeds and lower power consumption by adopting the leading edge processes for the circuit section

    By this stacked structure, large-scale circuits can now be mounted keeping small chip size. Furthermore, as the pixel section and circuit section are formed as independent chips, a manufacturing process can be adopted, enabling the pixel section to be specialized for higher image quality while the circuit section can be specialized for higher functionality, thus simultaneously achieving higher image quality, superior functionality and a more compact size. In addition, faster signal processing and lower power consumption can also be achieved through the use of leading process for the chip containing the circuits. Basically some of the attributes that we have been ranting about for 3DIC for the past 5 years. Samples will be shipped starting in March, 2012.


    Poly SI TSV found in the Toshiba BSI CIS from Fujifilm Camera

    Chipworks reverse engineering analysis of the Toshiba HEW4 BSI TCM5103PL 16 Mp, 1.4um Pixel Pitch CIS found inside Fujufilm F550 EXR camera. The CIS was fabricated using the Toshiba Oita 300 mm wafer line, using a 65 nm logic process adapted to BSI image sensor production. Fellow SST blogger Dick James [link] was kind enough to share more of the details for our IFTLE readers.

    With BSI, the I/O pads end up on the bottom side of the sensor silicon (which is bonded to a handle wafer so the pads are burried). To get to the pads, you need some means of creating a via through the silicon to the front side metal. Very high density arrays of polysilicon filled through silicon vias (TSVs), to form the electrical interconnect between the back side aluminum bond pads and the front side copper lines on the CMOS integrated circuits. These are the first true submicron TSVs that Chipworks has seen deployed in volume production.

    Chipworks notes that: "...closely packed, poly-filled submicron TSV... technology is non-trivial to implement. Once mastered and with appropriate economies of scale in play, however, this advanced TSV process saves valuable silicon area and can reduce the size of the camera module."



    Applied Materials Targets BSI Sensors Manufacturing

    Applied Materials recently announced the Applied Producer Optiva CVD system aimed at the manufacture of BSI sensors. "Emerging BSI image sensor designs present a new opportunity for Applied Materials to provide customers with the technology they need to be successful in this rapidly growing market"

    The Optiva low temperature process runs on their Producer platform, capable of depositing low temperature, conformal films that boost the low-light performance of the sensor while improving its durability. The system enhances the performance of the microlens by covering it with a tough, thin, transparent film layer that reduces reflections and scratches, and protects it from the environment. Importantly, the Optiva tool is the first CVD system to enable 95% conformal deposition at temperatures less than 200C. As typical bonding adhesives have thermal budgets of approximately 200C, all subsequent processing on these temporarily bonded wafers must be done below 200C.


    iSuppli estimates that 75% of all smartphones will be fitted with BSI sensors in 2014, up from just 14% in 2010. 2014 demand is estimated at 300 million units.

    Coming up in IFTLE:
    - Advanced packaging highlights from NEPCON Japan
    - 3D highlights from the IEEE 3DIC Conference in Japan

    For all the latest in 3D IC integration and advanced packaging stay linked to IFTLE........

    Hope to see you all at the IMAPS Device Packaging Conference in Arizona next month!
    IFTLE will be hosting a session on 2.5/3D Infrastructure development.


    IFTLE 88 Apple TSV Interposer rumors; Betting the Ranch ; TSV for Sony PS-4; Top Chip Fabricators in Last 25 Years

    February 11, 2012 10:58 AM by Garrou
    Apple about to Join the 2.5D TSV club?
    Click on any of the images to enlarge.
    It's not news that Apple has been considering moving fabrication of its A6 ARM processor from its current supplier Samsung to TSMC. The "A6," was scheduled to appear in the iPad 3 later in 2012. [link]

    By mid 2011 there were many reports that TSMC had started tooling up its 28 nm process to fabricate the A6 for Apple. The Apple A6 will be based on an ARM Quad Core Processor.


    Mid summer rumors were that the A6 would use "Intel 3D technology" technology , but recall this was the period in which several publications were totally confused over the difference between a finFET and a 3DIC [ see IFTLE 62, "3D and Interposers - Nomenclature Confusion..."] so I wasn't really sure what they meant.


    More recently statements like "The A6 is reportedly being built on TSMC's new 28nm process and incorporates the company's 3D chip-stacking technology. The use of through-silicon-vias (TSVs) and chip stacking could significantly improve the A6's power consumption compared to conventional planar silicon, but it adds a layer of complexity that could benefit from additional ramp time" make it much clearer that Apple is truly looking for 3D IC technology for their next generation products.[link]

    In fact EE Times has just reported that TSMC has had to do a "respin" on their A6 processor design and that "one potential reason of the respin is that TSMC plans to use 3-D stacking technologies along with its 28-nm manufacturing process in the production of the A6 for Apple. The use of a specialized silicon interposer and bump-on-trace interconnect may produce specific requirements in the main processor die." [link]

    Thus IFTLE now finds that it is highly likely that 2012 will bring us at least announcements (if not actual production) from Apple that their next processor will make use of 3D IC technology.


    How many IC Fabs are Ready to "Bet the Ranch"


    Growing up as part of the first TV generation in the USA (my family got its first TV in 1954 when I was in kindergarten), many psychologists have said that the impact of TV on my generation was profound. After Howdy Doody (a puppet show) and Crusader Rabbit (the first animated TV show by the group that later brought us the cult classic Rocky & Bullwinkle) my favorites shows were the westerns like "Have Gun will Travel" and "Rawhide" (which gave us Clint Eastwood). Part of all great westerns is the poker game in the saloon. The "good guy" (always in the white hat) is always the underdog and the "bad guy" (in the black hat) always has a table full of chips. When the good guy finally gets a hand that cannot be beat, the bad guy always bets more chips than the good guy has left on the table. That's when the good guy literally "bets the ranch (or maybe the farm)" on his unbeatable hand. Why he happened to be carrying the deed to his property in his back pocket was never actually explained. That phrase, "betting the ranch" has survived into today's lexicon and that's what a lot of microelectronic companies will be asked to do if they want to move forward with advanced technologies.



    IC Insights recently reported that Intel and Samsung plan $12.5 billion, $12.2 billion in capex respectively which is more than double the 2012 capex of TSMC (budgeted $6.0 billion). Combined, Intel, Samsung, and TSMC are forecast to account for about half of the total semiconductor capex spending in 2012.

    Samsung currently serves as Apple's foundry partner for the A4 and A5 application processors used in iPad tablet computers, iPhones, and iPod touch devices. Besides serving as a foundry partner for Apple, Samsung is aggressively ramping its in-house application processor business as demand increases for its smartphones, tablet PCs, and other mobile/media related devices. Meanwhile, the remaining $5.7 billion of Samsung's capex budget will be applied to the production of memory ICs, with a good portion of the funding likely to be used to boost capacity for NAND flash memory.



    Intel is nearing completion of, and will soon be equipping and ramping production at, three new wafer fabs located in Chandler, AZ, Hillsboro, OR, and in Ireland. The company plans to begin 14nm production in Chandler when that fab opens in 2013. The new Hillsboro facility will focus on process development using 450mm wafers when it begins operations in 2013. Meanwhile, several fabs will begin 22nm production in the second half of 2012.

    Samsung, Intel, and TSMC are positioning themselves as the strongest and most dominant IC suppliers in the industry and if anyone want to challenge that -- well they may have to bet the ranch! Weaker suppliers will be forced out of the business and a higher percentage of capex spending will be in the hands of the fewer remaining players.

    Sony says it wants TSV packaging for updated Playstation 3

    Masaaki Tsuruta, CTO of Sony Computer Entertainment, says that the company is working on a system-on-chip (SoC) for their fourth generation console which will not be called PlayStation 4. [link] The engine that powered the PS3 reportedly cost $400MM to develop; the main SoC for the new console could be the first $1bn hardware design project.



    Tsuruta indicated that there is likely to be a 3D stack incorporating TSV technology in the next generation console. Sony's target of no more than 50ms latency even for 8k x 4k resolution at 300fps, clearly points to the need for a highly integrated TSV-based package although Tsuruta warns "We will have to work with a lot of third-party partners to make these things happen."

    Noting the recent difficulties that several fabs are having trying to achieve viable yields at 28nm, Tsuruta commented that he believes that these problems are now moving towards a resolution.

    Semiconductor Leaders Over the Last 25+ Years

    Our friends over at IC Insights recently put together a Look at the Semiconductor Industries top 10 sales leaders over the past 25+ years. In case you haven't seen this, I thought you might like to take a look. You can interpret these results without any help from me.



    For all the latest on 3D IC and advanced packaging stay linked to IFTLE........................

    IFTLE 87 JEDEC Wide IO Stds, Elpida 3D shipments start while merger rumors loom , Renesas joins 3D wide IO Club; Comments from IBM on 22 nm & Beyond

    January 29, 2012 9:01 AM by Garrou
    JEDEC Wide IO Mobile DRAM Standards
    We have been talking about the JEDEC wide IO DRAM standards for a few years. [see IFTLE 19, "Semicon Taiwan 3D Forum Part 2"]

    Wide I/O mobile DRAM using 3D stacking with TSV provides "double the bandwidth at the same power, or can cut power in half at the same bandwidth" compared to LPDDR2 and LPDDR3. It is reportedly "particularly suited for applications requiring increased memory bandwidth up to 17GB/second, such as 3D gaming, HD video and user multitasking."

    Click on any of the images below to enlarge them.

    Well, the spec is finally finished and JESD229 Wide I/O Single Data Rate (SDR) can be downloaded from the JEDEC website [link]

    Wide I/O mobile DRAM enables 3D stacking with TSV interconnects and memory chips directly stacked upon a System on a Chip (SoC).
    


    The standard defines features, functionalities, AC and DC characteristics, and ball/signal assignments. The specification employs "LPDDR2-like" commands and timing parameters. The 512-bit memory interface has four independent 128 bits wide channels each operating at clock speeds to 266 MHz. resulting in a total bandwidth of 17 Gb/s for wide I/O SDRAMs (4.26 Gb/s/channel). The specification supports as many as four memory banks per channel, allowing die stacking of up to four wide I/O SDRAM die. The specification calls for 1.2V signal levels.

    The specification also standardizes:
    - Boundary scan testing (Boundary scan logic is integrated into the die for contact and I/O testing, providing full test coverage for contacts, drivers and receivers.)
    - Post-assembly DRAM test. (DRAM can be tested separately from the logic chip it's packaged with.)
    - Mechanical layout of the chip-to-chip interface.
    - Memory thermal sensor locations for DRAM, to provide reliable operation given thermal gradients introduced by logic chips.
    JESD229 does not control the bonding configuration between the memory and logic chips – i.e. side-by-side with interposer, or stacked memory on top of logic.

    The next generation of this Wide I/O SDRAM specification, already underway, will reportedly deliver eight times the performance and support 2.5D assembly.

    The JEDEC committee expects wide IO memory to be in mass production by 2014.
    Over the past 12-18 months we have seen wide IO adopted by all of the major memory players. Samsung [see IFTLE 40, "Samsung wide IO DRAM..."]; Elpida [see IFTLE 57 "Elpida and MOSIS Ready for 3DIC; TSV Going "Where the Sun Don't Shine"]; Micron [see IFTLE 38 "...of Memory Cubes and Ivy Bridges"]

    Elpida Starts Sample Shipments of wide IO Mobile DRAM
    In late December Elpida announced that it has begun sample shipments of 4-gigabit Wide IO Mobile DRAM which will deliver increased performance and lower power consumption, aiming these products at the smartphone and tablet device markets.

    By using x512-bit, a data width that is more than 10 times larger than the width for existing DRAMs, they enable a data transfer rate of 12.8 gigabytes per second (GB/s) per chip while operating at a low speed of 200MHz. The reduced DRAM speed results in approximately 50% less power consumption compared with DDR2 Mobile RAM (LPDDR2), currently the leading DRAM choice for mobile devices, configured at the same transfer rate. Elpida plans to begin volume production in 2012. Future plans are to develop two-layer 8-gigabit and four-layer 16-gigabit high-density packages for addition to the company's product line-up.[link]

    Elpida Facing Global Memory Consolidation
    There are only 6 significant DRAM suppliers left in the world: Samsung, Hynix, Micron, Elpida, Nanya, and Powerchip. Elpida, born of the consolidation of the DRAM businesses of NEC, Mitsubishi, and Hitachi in 1999, is the last remaining Japanese DRAM manufacturer. "Elpida" is Greek for "hope" and like the Greek economy, Elpida, the Japanese memory company, appears to be out of hope and financially on its last leg. The major problem is that many of Elpida's competitors have NAND to fall back on when the DRAM market is doing badly, but Elpida has only DRAM to keep itself alive.

    IFTLE views Elpida as one of the bright stars of 3DIC. Last fall IFTLE discussed the Business Week proposal that memory company consolidation was on the horizon [see IFTLE 69, "Cell Phones and Memory Consolidation"], how Elpida's financial outlook was grim and how Toshiba was the likely merger candidate. Digitimes reports that Elpida and Toshiba are in talks to merge their business operations. The merger is being "pushed" by the Japanese government, which reportedly wants Japan to keep its DRAM technology ownership on shore.

    [see Digitimes Jan 3rd, 2012 "Elpida and Toshiba Reportedly in Integration Talks"]

    Others are pointing towards talks between Elpida, Micron, and Nanya. Last week Reuters reported that Elpida is in talks to merge with U.S. firm Micron Technology and Taiwan's Nanya Technology. Elpida said it would not comment on rumors and speculation. [link]

    Micron has a 10-year agreement with Nanya (until 2018) to co-develop new DRAM chip technology. The two also run contract DRAM maker Inotera Memory via a joint venture. Nanya has posted losses for seven consecutive quarters but has been kept going by funds from its parent, the Formosa petrochemical group.

    Renesas to Commercialize TSV Technology for Wide I/O DRAM-compatible Mobile SoCs
    At the IC Packaging Technology Expo at NEPCON Japan in Tokyo, Renesas announced that it will apply TSV technology to its mobile SoCs so that they will support Wide I/O DRAM starting with mobile phone products. The DRAM will be stacked on the back of the SoC via 1,200 microbumps. The company plans to contract out the production of advanced SoCs to a silicon foundry as well as the production of TSV. [link]

    IBM Comments on 22 nm and Beyond
    Subu Iyer, IBM fellow, noticed that I have been using the IC consolidation slide (below ) shown by Handel Jones of Int Business Strategies (IBS) at the Semi ISS meeting in 2010. [see PFTLE 121, "IC Consolidation, Node Scaling and 3DIC"]

    Dr. Iyer informs IFTLE that IBM does not build a fab for every node except when there is a change in wafer size. "Our approach is to achieve a soft transition from one node to the other. As you may know we develop technology not just for IBM but also for Samsung, GF,ST and many others ... so as these development programs are complete, the SOI technologies are manufactured at IBM and the bulk technologies are transferred to our partners. Our current fab has transitioned from 130 to 90 to 65 to 45 to 32 nm in the last 10 years or so ... we expect this approach to continue. It is unlikely that we will outsource chips that we make for our mainframes, supercomputers etc. We only outsource OEM chips." IFTLE thanks Subu for that clarification.

    For all the latest on 3D IC and advanced packaging stay linked to IFTLE.....................

    IFTLE 86 3D Headlines at the RTI 3D ASIP part deux

    January 22, 2012 10:04 AM by Garrou
    Continuing  with key developments at the 2011 RTI ASIP
     ST Ericsson / CEA Leti / Cadence
    One of the best received presentations of the conference was “A Three-Layers 3D-IC Stack including Wide IO and a 3D NoC - a Practical Design Perspective –“ by Pascal Vivet, and Vincent Guérin. Going well past their allotted time during the scheduled presentation, they were brought back ( by yours truly) after the session ended to answer questions for a further 45 minutes. While some of the presentation was beyond the capability of the management and process development audience, the importance of the contribution was crystal clear to everyone.


     “Wioming” is the first application processor SOC integrated with a Wide I/O memory interface which should enable superior graphics and CPU performance in smartphones and tablets. It  is a high speed CMOS, TSV middle process with:
    - multicore CPU backbone
    - 4 wide IO memory controllers. Belived to be the first implementation of the JEDEC wide IO standard.
    - 3D asynchronous network on chip (NoC) for logic on logic stacking


    Scheduled for build are:


    - Uses ST-Microelectronics high-speed CMOS library                                                                    
    - Uses TSV middle (10μm) + Copper Pillar (10μm)                                                                                              - Flip-Chip packaging assembly                                                                                                                               - Face2Back, Die to Die 3D stacking assembly                                                                                                     - uses Cadence “Encounter 3D-IC” design implementation
    Was taped out in fall 2011 and is currently in fabrication.
    There is reportedly a ST Ericsson wide IO application processor product  in planning that will use TSV technology.  

    IBM

    Dan Berger IBM Manager of  “3Di” development reiterated a concept that we have heard before from IBM namely that “You need a bullet proof TSV formation process to make this all work” and that right now the “Supply chain is the toughest nut to crack – It’s good to be an IDM”. IBM is currently using 45 nm CMOS and 130 nm SiGe chip processes on a 2.5D interposer with 90 nm wiring for their Semtech products, announced last fall [ see IFTLE 27,“Era of 3D IC Has Arrived with Samsung Commercial Announcement”] which are produced in Fishkill  and their recently announced involvement with

     Micron on their memory cube commercialization [ see IFTLE 74, “The Micron Memory Cube Consortium” ].

    Yole Developpment
    Yole’s Perkins commenting on the TSMC statement pointed out that there’s lots of money in play here, and other people ( OSATS) aren’t going to just walk away, but are going to look for alternative solutions. The now annual Yole 3D timeline is updated below.

    STATSChipPAC [SCP]
    Raj Pendse, VP and CMO for SCP gave an in depth  presentation on their thoughts and approach to advanced packaging and 2.5/3D.

    Sematech
    Sematech’s  Arkalgud detailed the work at the Sematech “3D Enablement center” where the primary focus is on Wide IO DRAM for mobile and high performance applications.

       Their goal is to “..provide clarity and help identify gaps in standards, specifications and  technologies” Arkalud also indicated that Sematech is looking at next generation work on low time/temp Cu-Cu bonding technology that they are not at liberty to fully disclose yet.





    Without providing specifics, one of the conclusions from their Sematech cost analysis is that “3D interconnect can lower the overall cost of ICs
    ASE
    Hwang of ASE showed excellent electrical performance data for Cu bonded structures.


    Qualcomm
     Ray of Qualcomm said that they have determined that form factor and performance are the  most critical elements for them and that the smallest form factor comes from 3D stacking so they would most likely go directly to 3D stacking.  
    Synopsys
    Michael Jackson of Synopsis presented the following slide to rationalize why 2.5D is happening before  full 3D stacking.

    
    
    EVG
    Mathias of EVG updated their status on the Zonebond™ process . We have discussed the technical details of Zonebond previously [ see “Is 3D Packaging Where it Needsto Be?” ] The EVG position is that:
     EVG has worldwide access to Brewer Science  ZoneBONDTM technology, including:
     - The right to sublicense to any EVG equipment customers.
     - The right to produce carrier wafers and EVG equipment customers  to do so.
     EVG owns own IP related to the ZoneBONDTM process and to ZoneBONDTM equipment and as shown below the right to use any materials for the process including .
    - thermal release materials
    - UV/IR release materials
    - designated solvent release materials - thermal release materials
    - UV/IR release materials
    - designated solvent release materials

    For all the latest on 3DIC and advanced packaging stay linked to IFTLE…………………..


    IFTLE 85 2.5/3D Headlines at the 2011 RTI ASIP

    January 15, 2012 2:05 PM by Garrou
    Research Triangle Institutes 3-D Architectures for Semiconductor Integration and Packaging Conference, or 3D ASIP (as it has become known) normally finishes off the “3D conference circuit” for the year and is a good gauge of how far things have progressed in the last 12 months. At the 7th 3D ASIP in Burlingame CA a few weeks ago, there were several announcements, statements and rumors having significant impact on the 2.5/3D community.

    TSMC                                                                                           
    Much of the “buzz” at this years meeting certainly centered around the presentation by TSMCs Doug Yu a regular attendee of this meeting. Yu repeated the case he had made earlier at  the  Georgia Tech Interposer Conference [see IFTLE 80, “GIT @ GIT” ], for the pure foundry model for 2.5 and 3DIC,
    stating that TSMC was readying full beginning to end interposer manufacturing. Yu told the audience of more than 200 that sharing the fabrication process with OSATS was not the preferred option for TSMC because “…the risk for the customer is too high” and therefore TSMC would “ take full responsibility and accept full risk”. TSM is proposing that such one stop shopping ( at TSMC) will be simpler, cheaper and more reliable than using multiple sources (i.e. foundries, assembly houses and potentially other partners). Since the profit margin for packaging and assembly is currently substantially less than that for a foundry like TSMC manufacturing chips, cost sensitive customers appeared worried that packaging and assembly costs would increase substantially if turned over to foundries. Yu remained steadfast in his assessment that the required investments and the technology needed to handle thinned wafers would require that the foundries take control of such processing. “This is a new ballgame, the old ways of doing business are out of date for this new technology” Yu reiterated. Rumored to be currently working with only a handful of 2.5D/3D customers ( including Xilinx), Yu indicated that “…new customers will have only the  integrated solution proposal…..some, but not all of them [customers] want us to work with other partners, but many like our new approach very much".
    Certainly with their customer Xilinx being first to enter the market with their 2.5D based Virtex 2000T FPGA, TSMC appears ahead of the rest of the foundries in this regard. Currently, TSMC is manufacturing the Xilinx chips and manufacturing and bumping the Xilinx interposer. Xilinx is using Amkor to assemble the FPGA chips on the interposer and the interposer onto a BGA package.  Since the interposers are using 65 nm dual damascene processing for the multiple layers of RDL, in reality this is something that  the assembly houses currently aren’t equipped to handle. More on that below.

    When asked about the incorporation of other foundries chips onto the interposer or chip stack, Yu responded that there is no need to go to other foundries / IDMs except for memory, and that TSMC would partner with one or more memory suppliers to have that issue resolved.
                                        Cho (Samsung) and Yu (TSMC) enjoying lunch at ASIP.                                
      Is Samsung a potential 2.5/3D partner for TSMC ?  
    Microelectronic Consultants of NC
    During my presentation detailing the status of 3DIC entering 2012, the issue of interposer categories came up. Basically interposers can be categorized as either being high density l/s ~ 1µm /1 µm which could only be manufactured by CMOS fabs/foundries and what we can call “coarse” featured interposers with l/s > 5 µm / 5 µm. The latter could be fabricated by ay of the OSATS who all have standard bumping and WLP processes capable of standard RDL. In a later presentation (IFTLE 86 next week) Raj Pendse of STATSChipPAC indicated that 5 um l/s and sub 25um TSV pitch was the transition point between OSAT and foundry capability

    
    While all the OSATS have such capability, products have not yet been announced that would use such course dimensioned interposers and none of the OSATS have announced any intention to produce any interposers.   One OSAT requesting anonymity later commented “It is correct that we are not offering “coarse” interposers , although we have capability to produce them – this is because we don’t see ourselves competing in that space with foundries and don’t think it will be a viable biz worth chasing and investing capital and resources in”. Eric Beyne, I MEC, during his presentation also questioned whether coarse interposers would provide enough value to be integrated into products.  Similar responses were received from other OSATS in attendance.
    Despite those comments, unsubstantiated rumors swirled at the conference that Siliconware had or was about to purchase a complete 2.5D/3D line from Applied Materials which included dual damascene capability so they could enter into manufacturing of high density interposers. Neither Applied nor Siliconware [SPIL] would confirm or deny the rumors, but it was interesting that SPIL customer, graphics chip maker NVIDIA in their presentation (see below) indicated that they would require 2.5D soon.
    If the SPIL rumor is true, such a play might force other OSATS to follow suite….we shall see.
    NVIDIA
    LeiLei Zhang, of NVIDIA, made what could become the rallying cry of the upcoming 3D decade when she said  Scaling is ending. Let’s get over it and move our resources elsewhere.” Zhang declared that for them bandwidth is the issue. She indicated that NVIDIA is likely to use a turnkey solution such as TSMC is offering with such 2.5D TSV solutions entering the NVIDIA roadmap with their TESLA and CUDA high end networking GPU product lines.   

    
    Although she wouldn’t indicate who her fabricator partner was, Zhang detailed the Nvidia Interposer program Status as follows:
    - Demonstrated working process on very difficult test vehicles
    - Reliability data looks OK but limited
    - Long development cycle time
    - Need more industry resources – both equipment and manpower
    - Thin wafer Transport not Advised
    - Assembly yield limited by Interposer warpage
    - Non-wetting µbump
    - Need Assembly Process, die thickness, µbump, materials optimization
    - Biz model unclear
    - Must choose between traditional supply chain & full turnkey solutions
    Xilinx
    Ivo Bolsens VP and  CTO of Xilinx detailed their Virtex 2000T FPGA which he claims delivers 4X the compute performance  as the current largest monolithic device. IFTLE has previously covered the performance of this device in detail. [ see IFTLE 73, “Xilinx shows 2.5DVirtex 7 at IMAPS 2011” ]
    Altera
     While Altera’s Bradley Howe predicted that “…there are 8-10 years left to scaling, and then 3D will be the solution” he was quick to show 2.5D prototypes they are reading for the market, evidently a lot earlier than that. With arch rival Xilinx already sampling the market with 2.5D products that’s probably a good idea.

    Seen at the RTI ASIP:

    
    Next week we will finish up coverae of RTI ASIP. For all the latest in 3DIC and advanced packaging stay linked to IFTLE………
            

    IFTLE 84 .... and the Winner is

    January 7, 2012 11:05 AM by Garrou
    Well, all the ballots have been cast. The winner of our contest was determined by who could correctly identify the most  faces that they had seen previously in the pages of  PFTLE/IFTLE …and the winner is...... Dr. Beth Kesser of Qualcomm who correctly identified 38 .


    Dr Kesser was shipped MRS volume 970 "Enabling Technologies for 3D Integration" edited by Bower, Garrou, Ramm and Takahashi. Beth received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. in Materials Science and Engineering at the University of Illinois at Urbana-Champaign. Beth's interests include developing materials and packaging technologies for the semiconductor industry, which has resulted in 7 patents, 5 patents pending, and over 33 publications in this area. Currently, Beth is the Wafer Level Packaging Product and Technology Manager at Qualcomm in San Diego. Also, Beth is the Assistant Program Chair of the 62nd ECTC to be held in San Diego, CA in May 2012 and was just elected to the IEEE CPMT Board of Governors. 


     The correct names and affiliations are shown below:


     A few fun points:
    1) Most recognizable were Jack Nicholson (every single ballot got Nicholson correct!), Dora, Koyanagi-san, Morris Chang, Bob Patti and my granddaughter .
    2) Most misspelled name - Ron Homuler or is it Huemoller or as one respondant labeled him  hummuler. Ron - They knew who you were but had trouble with the spelling!
    For all the latest in 3DIC and advanced packaging stay linked to IFTLE..........

    IFTLE 83 Orange County IEEE CPMT 3DIC Workshop

    January 7, 2012 10:57 AM by Garrou
    In early December the Orange County chapter of IEEE CPMT held a 1 day workshop entitled "3D Integrated Circuits: Technologies Enabling the Revolution," which included presentations by Xilinx, IMEC, Mentor Graphics, FCI, Microelectronic Consultants of NC, STATSChipPAC, Henkel, EPWorks and Apache (Ansys). The General Chair was Larry Williams from Ansys and the technical chairs were Don Frye from Henkel, Bob Warren from Conexent and Sam Karikalan from Broadcom. In the true spirit of information sharing, the intentionally low fee of $40 drew over 200 attendees for the event.



    Eric Beyne of IMEC took a look at 3D challenges and progress. The standard IMEC TSV are 5 x 50um for 3D stacking moving in the future to 3 x 50 and for 10 x 100 for 2.5D interposers.

    Beyne notes that nearly all options for debonding from carrier wafers are moving to RT solutions. The previously well accepted slide debonding has a small process window and is difficult with bumps on the glued interface. Brewer Science in conjunction with EVG and Suss Microtech are now promoting the Zonebond process which uses a RT release process.

    As a cost reduction option, IMEC is studying the elimination of the CMP process for wafer thinning to 2um TTV on 300mm wafer down to 50um thickness. Beyne favors laminated WUF (wafer level underfilling) vs NUF (no flow underfill pre applied to the substrate) commenting that "Probably lamination is the way to go since it covers the fragile ubumps with UF before the assembly process so it's better to handle." In addition one achieves lower surface topography using WUF.
    Ted Tessier, CTO of Flip Chip Int (FCI) addressed their embedded die packaging JV with Fujikura. Fujikura’s “WABE” technology (Wafer And Board Level Device Embedded technology) involves stacking and lamination of multiple layers of Cu/PI printed circuit layers around embedded, thinned die and passive components and via filling with conductive paste. Packages can be fabricated in either a face up or face down orientation with backside thermal via options available for improved thermal performance. Multiple die and passive components can be integrated at die spacing as tight as 100um. Passive components can be embedded as well. Processing panel size is currently 250 x 350mm.

    Prof Muhannad Bakir of GaTech addressed his specialty 3D stacking with liquid cooling where significant reductions in power and temperature can be achieved. Most agree that some sort of liquid cooling will be necessary for server farms in the future to reduce power usage.


    Stephen Pateras of Mentor Graphics looked at the challenges and solutions for 3DIC test.


    Gusung Kim CE of EPWorks, the Korean startup offering interposers indicated that customers want interposers at the same prince as high end laminate, i.e. $300/wafer for a 300 mm wafer of interposers. Kim offers glass interposers but sees most programs currently moving forward on silicon. He sees 100 um TGV (through glass vias) doable (in 100 thick glass) , but customers are asking for 10 um TGV.
    David Butler, VP of Marketing for SPTS gave a nice update on their equipment for Via Reveal - High Rate Si Thinning and Low Temperature Dielectrics for Post-TSV Processing.
    

    SPTS recommends stopping the grind ~5-10um above the TSV so you don’t expose Cu because exposed Cu would migrate. Then one selectively etches Si to ~5-7um below the oxide cap without removing the oxide. The surface is then coated with nitride (for migration barrier) and then oxide, then, after resist definition, Cu is exposed by oxide etching and RDL is built upon the exposed Cu studs.
    In the SPTS tool different etch modes are used to control the etch uniformity which reportedly is typically +/-4% with a built-in etch stop process.
    


    
    Low Temperature (175C deposition ) SiN Barrier is in 300mm production on CMOS image sensor. It is reportedly a dense film with <100MPa residual stress and excellent adhesion and electrical properties. Low Temperature PE-TEOS SiO2 is deposited at 175C with low leakage and high breakdown voltage. Etch and deposition are available on one or multiple platforms.

    Coming up next -- an extensive review of the RTI 3D ASIP Conference.........

    For all the latest in 3DIC and advanced packaging stay linked to IFTLE.............

    IFTLE 82 3DIC at the 2011 IEEE IEDM and other 3D and Adv Pkging topics

    January 1, 2012 4:50 PM by Garrou
    My Christmas and New Years time off was great; hope yours was too. Hannah and Madeline got their letters of to Santa and I had a great Texas Christmas with the grandaughters.



    ...and now back to 2011 conference coverage...

    2011 IEDM

    3DIC presentations at the recent IEEE IEDM Conference focused on potential reliability concerns.

    ST Micro / Leti reported on two potential reliability issues for direct bond copper -- namely stress induced voiding and electromigration. Electromigration (EM) and stress-induced voiding (SIV) testing was performed on bonded daisy chains to investigate the reliability of the structures. Test vehicles were wafers bonded at room temperature, atmospheric pressure, and ambient air and then annealed at 200°C or 400°C to strengthen the bonding.

    In some NIST-type devices, they observed voids at the cathode side and copper extrusion next to the anode pads after 200°C post-bonding anneal and exposure to 325°-350°C and 3-3.5 MA/cm2. Time-to-failure (TTF) is defined as a 10% resistance variation. They make arguments to support the conclusion that the Cu-TiN interface appears to be the dominant pathway for EM -- not the Cu-Cu bonded interface as might be expected. On some tested die they observed voids and copper extrusion on both opposite sides of the daisy chain showing that the structure acts as one continuous interconnect without interface separation between copper lines on the two bonded levels. In standard copper interconnects and vias chains, each copper line is separated by the metallic barrier between the line and the vias.

    SIV testing of the daisy chains interconnected by direct copper bonding process after 400°C anneal and thermal stressing at 175°C-200°C and a current of 1mA for 2000hrs showed no degradation, i.e. less than 5% resistance change for all the tested samples.

    They conclude that: "Direct copper bonding does not impact on the failure mechanisms concerning Cu interconnect reliability."

    Koyanagi-san and his group at Tohoku University reported on their studies on W / Cu hybrid TSVs. They propose that high-density 3D-LSI die requires more than 104-105 μbumps and TSVs per chip and die thickness of <10μm with near zero remnant stress. Due to this, W TSVs may outperform Cu TSVs not only due to their ability to form sub-micron vias, but also since W does not diffuse in silicon the way Cu does, and leaves very minimum stress in active Si owing to smaller difference in CTE between W and Si. Therefore, W-TSV is preferable for high-density and high-speed TSVs with small diameter and small capacitance for signal lines.

    However, W-TSV is not as suitable for power/ground (GND) lines because of its higher resistance. Cu-TSV with larger diameter and lower resistance should be employed for TSVs for power/GND lines. Cu-TSVs with larger diameter are also more preferable to suppress Cu diffusion since a barrier metal such as Ta can be conformally and uniformly formed into deep trench for TSV which effectively suppresses Cu diffusion. One can also suppress the influences of Cu diffusion on device characteristics by placing Cu-TSVs for power/GND lines apart from the active areas. Thus, the Tohoku group proposes a high-density 3D-LSI using W/Cu hybrid TSVs.



    μ-Raman spectroscopy revealed that mechanical stresses increase with an increase in TSV diameter for both Cu- and W-TSV. They conclude that Cu-TSV with the size of <10μm and W-TSV with the size of <1μm leave only compressive stress in the TSV spacing region when the TSV pitch was smaller than twice of TSV size. It is important to increase the TSV pitch to larger than 2× the TSV size to avoid peeling (inside the via), extrusion of the via metals, and cracking of the LSI die. Residual stress in thinned die changes from compressive stress for the die/wafer thickness of >100μm to tensile for thicknesses <30μm. They warn that "tensile stress leads to die-cracking due to weakening of Si-Si bond, which is a threatening issue in 3D-LSIs."

    Farooq of IBM detailed their reliability studies (thermal cycling >500 cycles) and thermal stress (>275°C for 1500 hr) on 3D modules built by integrating Cu TSVs with high-k/metal gate and embedded DRAM.

    They found no degradation of TSV or BEOL structures, and show that there is no significant impact on device characteristics from TSV processing and/or proximity.

    TSVs were integrated at fatwire (upper metal) levels to optimize wire-ability and process complexity with 4 to 12 metal levels including low-k interlevel dielectric (ILD), built on SOI and bulk Si wafers. TSV of <100μm depth were etched with near vertical sidewalls at a minimum pitch of 50μm. An example of this is shown below.



    TSV and BEOL structures did not degrade after 500 thermal cycles (-65°C-150°C), and no change in either the leakage or the wiring resistance was observed. Structures consisting of wiring and via chains above and near the TSV also showed no degradation after thermal cycling. Wafers baked at 175°C-275°C for 1500hrs showed no voiding or delamination occurred near TSVs. Frontside and backside wiring levels on a thinned wafer were connected with TSVs to create chains of 3000 links; the chains showed no change in resistance after 500 thermal cycles.



    TSV insulator breakdown voltages of 250V-300V were observed.

    They observed that significant shifts in device characteristics were possible for some processing conditions, in particular "FET Vt was shifted under certain etch conditions" but optimizing the etch process minimized this impact. In general, they concluded: "With optimized design and processing, stress fields associated with TSVs are significantly lower than those required for strain engineering of the devices, and are not expected to shift device characteristics."

    More detail is available here [link].

    Honeywell and Tezzaron to build rad hard 3D-ICs

    Honeywell Microelectronics and Tezzaron Semiconductor have announced that they will be working together to produce radiation-hardened 3D integrated circuits. Honeywell's S150 process will use Tezzaron's 3D stacking to greatly increase circuit density without migrating to a smaller node. The resulting three-dimensional integrated circuits (3D-ICs) are also expected to use much less power than their 2D counterparts. Tezzaron CTO Bob Patti commented: "Memory can now be integrated vertically rather than embedded in the logic die. The current practical limit is around 32 Megabits, but 3D could put as much as 4 Gigabits of high-quality DRAM onto a single rad hard chip."

    Tezzaron also announced a research collaboration agreement with the A*STAR Institute of Microelectronics (IME). The two organizations will improve and refine the design and manufacture of silicon interposers and work to standardize the process, flows, and process design kits (PDKs). Initial early production devices are already in development, based on IME's TSI (through silicon interposer) technology and incorporating 3D-ICs from Tezzaron. Fabrication will be completed in IME's state-of-the-art 300mm R&D fab. The resulting TSI technology from the collaboration will form the foundation for the TSI Consortium driven by IME, to be launched in early 2012.

    IME and Tezzaron have a history of cooperation dating back to 2001, when IME provided its copper line technologies to Tezzaron for their wafer stacking endeavors.

    LED testing update

    We are now 4+ months into our lightbulb testing and I am happy to report that both bulbs (LED and CFL) continue to burn bright -- as well they should, since you will recall the average life of an incandescent is ~1 year. [ see IFTLE 63, "Bidding adieu to Lester Lightbulb."

    I have come across an interesting article which tries to explain the new light bulb test protocols and adds to what I tried to explain [link].

    The winner of the contest will be announced next week -- along with the answers to who all those people were!

    For all the latest in 3DIC technology and advanced packaging stay linked to IFTLE..........
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