IFTLE 156 2013 ConFab part 1 Sony, IBM, TI, SCP

    July 28, 2013 9:33 AM by Garrou
    Those of you that are readers of SST know from the editorials and blogs of  Editor Pete Singer that the ConFab is  Solid State Technology's annual conference and networking event. This year, it was held in June 23-26 in Las Vegas.  The overall theme of this year’s conference is “Filling the fabs of the future,”

    IFTLE  put together two sessions on packaging  which were jointly sponsored by IEEE CPMT and ConFab.

    The most significant packaging announcement from the ConFab was SPIL announcing that they have put dual damascene in place and are ready to start supplying high density interposers to the industry. [see “Siliconware announces entrance into high density 2.5D interposer market”].

    Sony CMOS Image Sensor 3D Stacking

    Fellow bearded blogger Dick James of Chipworks, in his presentation “inside Todays Hot Products” showed some great X sections of the Sony IMX135 13 Mpixel CMOS Image sensor. One of the first stacked image sensors it consists of a 90nm back illuminated sensor bonded F2F with a 65nm image processor

     
    IBM Orthogonal Scaling
    Subu Iyer , IBM Fellow, lectured on his theme of “orthogonal scaling” . His premise is that classical silicon scaling is saturating and we need orthogonal approaches to “scale all aspects of the system including footprint and power”. Subu sees scaling continuing down to the 7nm node, but  “the cost per transistor has begun to saturate”
     
     
     
    He predicts that the next component of Advanced System Integration will be 3D Integration:
    - large interposer platform for heterogeneous integration    
     
    - Die Stacking
                   - stacking of logic die (high and moderate power) 
                   - stacking of memory die (low power)
    - Wafer level stacking
    His example of stacked memory is the Micron IBM program on stacked memory:
     
     
    TI Thins Down Packaging
    Devan Iyer, worldwide Dir. of Packaging for TI showed the thickness progression from the 1.75mm SOIC to the 0.075mm PicoStar-2G
     
    Iyer points out that while Package families are  proliferating, each package type has a “sweet spot” combination of cost, performance, form factor and reliability, driven by:
    •Cost
    •Electrical speed, power distribution and noise immunity
    •Power dissipation
    •Thickness, weight, PCB area consumption
    •Board level reliability (BLR, drop)
    •Environmental reliability
    •Technical maturity vs. risk in high-volume manufacturing
    •Testability
    •Compatibility with Si process
    STATS
    Anderson of STATSChipPAC  points to smartphones and tablets driving our industry right now.
    
     
     
    For all the latest on 3DIC and Advanced Packaging stay linked to IFTLE.........
    
     
     
     
     
     
     
     
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