When front-end-of-line and back-end-of-line reliability meet

Due to the further scaling and increasing complexity of transistors, the boundaries between back-end-of-line and front-end-of-line reliability research are gradually fading. Imec’s team leaders Kristof Croes and Dimitri Linten give their vision on the future of reliability research.

In April 2015, the 53rd edition of the IEEE International Reliability Physics Symposium (IRPS) took place, a top conference where experts in reliability of micro- and nanoelectronics meet. With 16 contributions as either an author or a co-author, imec was prominently present.

Dimitri Linten: “Our contributions to conferences such as IRPS highlight the unique role that imec plays in the field of reliability. And they show the importance of reliability research at imec for the development of new transistor and memory concepts. As scaling continues, a whole range of new technology options is being researched. New materials and architectures with often unknown failure mechanisms are being introduced. Reliability is one of the factors that determine which concept will finally have a chance. For example, one of the options is to replace silicon in the transistor’s channel by germanium or a III/V material since these materials provide a higher charge carrier mobility. But until now, these materials pose important challenges to the reliability of the transistors that are made of these materials. Or, researchers look at introducing either air gaps or ultralow-k materials as spacers between the transistor’s gate and drain in order to keep the capacity as low as possible. The integration of all these new materials is important, but their reliability is crucial as well: reliability before performance.”

Kristof Croes: “10 years ago, reliability was tested only in a final stage of a technology development. But due to the ever decreasing reliability margins, the reliability is now being tested from the very beginning. And this starts with an understanding of the physics behind the failure, for which we often collaborate with universities. Once we understand the failure of e.g. new materials, we can model our findings and predict the lifetime of the device.”

Front-end-of-line vs back-end-of-line

Traditionally, CMOS process engineers classify the semiconductor process in two main parts: the front-end-of-line (FEOL) and the back-end-of-line (BEOL). The FEOL comprises all the process steps that are related to the transistor itself, including the gate of the transistor. The BEOL comprises all subsequent process steps. In the BEOL, the various transistors are being interconnected through metal lines. The same classification is being used in reliability research. Consequently, FEOL and BEOL reliability is tested independently.

Kristof Croes: “This historical separation is being applied at imec as well, where reliability research within the process technology division is distributed among several groups. One group looks into the reliability of FEOL and memory chips. Another group investigates the BEOL reliability and chip packaging interaction. Today, in BEOL processes, electromigration (the movement of metal atoms as a result of an electric current), stress migration, time dependent dielectric breakdown (TDDB) and thermomechanical stress are the main failure mechanisms. We also look into 3D structures, where the impact and reliability of through-Si vias are important issues. In a 3D-stacked structure, for some applications, the Si wafer needs to be thinned down to about 5 micrometer. And this impacts the reliability. And there are thermal and thermo-mechanical influences related to the assembly of materials with completely different mechanical properties. All these failure mechanisms in the BEOL will become increasingly important for future technology nodes.”

Dimitri Linten: “We look into the time dependent breakdown (TDDB) of the gate stack, and into stress-induced leakage current (SILC) and hot carrier stress (HC). The bias temperature instability (BTI) is important as well, as it causes a shift of the threshold voltage (VT) of the transistor during the lifetime of the circuit. We also investigate memory elements, by testing and modelling the retention and endurance of the memories. ESD or electrostatic discharge is still one of the main important failure mechanisms at the level of the final ICs in a certain technology. In order to intercept the current that is released during an electrostatic discharge, protecting ESD structures are implemented in the FEOL.”

FEOL and BEOL reliability: fading boundaries

As the dimensions of the transistor shrink, the impact of the FEOL on the BEOL reliability – and vice versa – increases. Kristof Croes: “A well-known example is self-heating in FinFETs. In planar CMOS processes, the heat that is released during the transistor’s operation is dissipated mainly through the Si substrate. But in a FinFET architecture, we have to take into account a higher thermal coupling towards the metal intercon- nects. The FinFETs warm up and heat the metal lines. And this impacts the reliability of the BEOL structure. In 3D technology, we thin down wafers with TSVs. After opening the TSVs, we can stack them on top of another wafer. The integration of the TSVs, the thinning and stacking of the wafers influence both the FEOL and the BEOL performance and reliability.”

Dimitri Linten: “Also the introduction of new architectures brings the reliability of FEOL and BEOL closer to each other. Think about vertical nanowires, potential successors of the FinFET because they promise a better electro- static channel control. One of the challenges in terms of reliability is to provide these structures with an ESD protection. While in more conventional structures, the FEOL is most sensitive to electrostatic discharge, the impact of electrostatic discharge on the BEOL becomes critical in vertical nanowires. In these 3D structures, we have to connect all the vertical nanowires through local interconnects and interconnects that will be located very close to each other. And these interconnects will put other requirements to the ESD protection circuit than we are used to. A possible solution is to consider a 3D stacking of ESD protection circuits on top of the transistor architecture.”

Another consequence of further scaling is an increase in the variability of the transistor parameters. In FEOL, variability is a well-known phenomenon.

Dimitri Linten: “Time dependent variability of BTI is a relatively new challenge for reliability research. For large transistors – the older generations – BTI translates into an average shift of the circuit’s threshold voltage of e.g. 50mV, the spec for BTI. But upon further scaling, there is no average shift anymore. Instead, there will be a static distribution of shifts. The variability becomes time dependent and the lifetime of the circuits will be spread. The imec FEOL reliability group is a world leader in this domain: we have developed a defect centric BTI model that has been adopted by market leaders in the semiconductor industry. On time dependent BTI, we closely collaborate with the design group in order to develop methodologies that take into account the time dependence.”

Kristof Croes: “Also in BEOL, variability becomes increasingly important. Think about via misalignment or line edge roughness of increasingly smaller metal lines. These issues degrade the reliability and the lifetime of the BEOL. To deal with the increasing variability, a powerful statistical toolbox is required. And this toolbox can be deployed for BEOL as well as for FEOL reliability research.”

When BEOL meets FEOL reliability

As dimensions are shrinking, the boundaries between FEOL and BEOL reliability are gradually fading.

Kristof Croes: “We are convinced that we should optimally attune the activities and tools used for reliability research. We have to bring the people from BEOL and FEOL reliability closer together. And we want to unite the researchers outside these groups that work on reliability. Reliability is a field of expertise and sharing problems often provides part of the solution. For future technology nodes and for develop- ments beyond scaling, this will increase the operational efficiency of reliability research. To strengthen this idea, we will organize an internal workshop at imec on September 4, with the help of our predecessors and colleagues Guido Groeseneken and Ingrid De Wolf. This will help our researchers to gain more insight into each other’s work and into the tools they use. Hopefully, this idea will be adopted outside of imec as well.”

Additional reading

Technical program of the 2015 IRPS conference with abstracts (http://www.irps.org/program/technical-program/15-program.pdf)

“New test allows to visualize in real-time crack formation of BEOL,” March issue of imec magazine (http://magazine.imec.be/data/57/ reader/reader.html#preferred/1/package/57/pub/63/page/2)


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