What chipmakers will need to address growing complexity, cost of IC design and yield ramps

Bruno Mourey, chef du Département intégration hétérogène sur siliciumBy Bruno Mourey, Chief Technology Officer, CEA-Leti

As these early days of the Internet of Things show the network’s promise and reveal technological challenges that could threaten its ability to meet user expectations in the years ahead, technology providers will be charged with supplying the solutions that will meet those challenges.

Chief among them for designers and chipmakers are the increased complexity and cost of IC design and yield ramp-ups, and wafer costs, said Carlo Reita, strategic marketing manager at CEA-Leti.

“Disruptive architecture and integration technologies are required,” Reita told participants at the 17th annual LetiDays in Grenoble, France, June 24-25. In his talk, “Technologies and architectures for low-power data processing,” Reita noted the spikes in both complexity and cost that accompany the industry’s progression to smaller technology nodes. The spikes are driven primarily by costly new tools and increases in both design manpower and the number of expensive licenses for software-design tools that accompany increasing device complexity.

Reita cited projections from IBS that industry-wide, non-recurring engineering (NRE) costs will total $38 million for IC designs at the 28nm node, $132 million at the 16nm node and $1.34 billion at the 5nm node.

Adding yield ramp-up costs to IC design costs, which include both new designs and specializations, the projected NREs skyrocket from $59 million at 28nm to $176 million at 16nm and $2.24 billion at 5nm. Meanwhile, the average selling price of 300mm wafers grow from $9,885 at 16nm to $19,620 at 5nm.

Reita noted that such projections underscore the pressure that the industry will face to develop new design-implementation approaches that change the cost metrics for advanced-features, so that initial products can generate revenues that justify the design and yield ramp-up costs.

He said that managing data traffic that is increasing exponentially, while maintaining data-center server performance and lowering the centers’ energy consumption, is among the top challenges for the computing industry in the years ahead. Meanwhile, mobile computing and the Internet of Things are adding a different set of challenges that will feed the design-cost escalation, ranging from the requirement for mandatory long battery life to supporting heterogeneous and power-hungry applications and the capability to adjust to process, voltage and temperature variations.

Reita also outlined Leti’s plans and vision for technologies that address these challenges in the short, medium and longer terms.

Like other speakers during the two-day event, he noted FD-SOI’s advantages compared to FinFET as a proven low-power, cost-effective solution that will meet current and mid-term needs for devices down to the 10nm node. In addition, transistor-stacking options, such as Leti’s low-temperature CoolCube technology, support denser and higher-performing CMOS devices. CoolCube also makes it easier for designers to use heterogeneous integration of material and/or functions and provides a greater degree of freedom for design partitioning, Reita said.

Other avenues of exploration include adaptive fine-grain architecture that mitigates local and dynamic PVT variations, and permits either better use of the chip surface or smaller chips

Leti also is working on resistive RAM that can reduce power consumption at the storage level by putting high-density, non-volatile memory closer to logic chips.

On Leti’s roadmap for the medium term, neuromorphic architectures may enable full transfer of successful algorithms into a specific physical system that will achieve power-efficient computation. Deep recurrent networks with spike coding are a likely candidate to best match physical implementation characteristics.

In Leti’s view, this architecture also allows co-localization of memory and computation similar to a biological system, where a synaptic element performs storage, interconnect and non-linear operations. In addition, the architecture takes full advantage of Leti’s advanced RRAM, 3D and low-power CMOS techniques to break memory-bottleneck and synaptic-density issues, while maintaining ultra low power.

Reita also spoke briefly about quantum computing, “a very long-term” technology possibility, whose appeal includes superposition of the quantum bits (qubits) states in an ultimate parallel system and reversible operators that keep power use at a minimum. This architecture, which is probably 20 years down the road, is expected to massively accelerate computation. It will be best suited for tackling complex optimization problems, Reita said.

Leti collaborates with CEA’s fundamental research departments on topics including SiGe nanowire devices, in which electronics states can act as qubits and use Pauli spin blockade for spin-charge conversion and interaction with CMOS and the external world.

Related news:

Leti workshop covers major trends in FD-SOI technologies

ASCENT project offers unparalleled access to European nanoelectronics infrastructure

Leti launches new Silicon Impulse FD-SOI Development Program


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