A*STAR’s Institute of Microelectronics (IME), together with Amkor Technologies, NANIUM, STATS ChipPAC, NXP Semiconductors, GLOBALFOUNDRIES, Kulicke & Soffa, Applied Materials, Inc., Dipsol Chemicals, JSR Corporation, KLA-Tencor, Kingyoup Optronics, Orbotech and Tokyo Ohka Kogyo have formed a High-Density Fan-Out Wafer Level Packaging (FOWLP) consortium to extend FOWLP capabilities for applications in devices such as smart phones, tablets, navigation tools and gaming consoles.
These devices call for application processors with greater system capabilities such as increased memory and bandwidth, as well as faster processing speed to support myriad demanding applications and functions, while consuming low power. At the same time, the sheer market volume1 for such devices necessitates system cost reduction.
FOWLP is a low-cost packaging technology for system scaling which enables multiple chips to be integrated in a small form factor on a single package. However, the adoption of conventional FOWLP technology for high performance, multi-functional devices is being challenged by pin-count density of a few hundreds of I/Os per device package. These limitations have a direct impact on its capability to support increased system requirements and performance.
The consortium aims to provide solutions to overcome these limitations. It will develop a High-Density FOWLP test vehicle capable of supporting thousands of I/Os and characterising the package for die shift, die protrusion and wafer warpage analysis that will enable system scaling for smartphones and mobile tablets. Concurrently, tight wiring to accommodate increased pin counts using fine pitch multi-layer redistribution layer technology will be demonstrated for large area FOWLP while maintaining its signal/power integrity and reliability.
“System integration is necessary to enable diverse functionalities with high performance in future applications across a wide spectrum of industries including computing and networking, healthcare, consumer electronics, transport and automotive. With the High-Density Fan-Out Wafer Level Packaging consortium, IME continues to add to its portfolio of advanced packaging platforms so as to provide wide-ranging solutions for the continued evolution and different needs of complex and demanding devices,” said Prof. Dim-Lee Kwong, Executive Director of IME.
“Amkor is pleased to participate in the High-Density FOWLP consortium to help accelerate the adoption of this next-generation package platform technology. As a leader in the space, working to drive packaging and test technologies forward is one of our core objectives. We expect advanced platforms like High-Density FOWLP to become the prevailing packaging format for much of the advanced integration market, including mobile and high performance products,” said Mr. Ron Huemoeller, Senior Vice President, Advanced Product & Technology Development, IP of Amkor Technology, Inc.
“Market applications will always be our industry’s main drivers,” commented Mr. Armando Tavares, President of the Executive Board at NANIUM. “In times of More-than-Moore, I/Os requirements have been increasing steadily, as they translate into higher integration, improved performance, minimal form-factor and cost-effectiveness. The development of High-Density Fan-Out Wafer-Level Packaging technology represents a step towards fine-pitch multi-layer redistribution, which in turn will allow us to build higher-density structures. These will significantly increase the amount of interconnects enabled by FOWLP, turning this technology into an IC packaging platform for chip-to-chip interconnect with a higher I/O and at a competitive cost.
NANIUM regards IME’s initiative of creating a consortium as a very insightful one. Through the combination of our know-how and manufacturing capabilities with IME’s technology development expertise, we will surely contribute to the development of our FOWLP technology roadmap, to the benefit of our customers.”
“High-Density Wafer-Level Fan-Out Packaging technology enables advanced system scaling for form factor limited and cost challenged applications,” said Mr. Ramakanth Alapati, Director of Package Architecture and Customer Technology at GLOBALFOUNDRIES. “GLOBALFOUNDRIES appreciates IME’s effort to identify robust solutions needed for a cost-effective high volume manufacturing approach to wafer level packaging.”
“The strong collection of companies who have joined the consortium and our shared commitment to expanding the capabilities of FOWLP reflects the promising value of this technology for a wide range of high performance applications. This collaboration will accelerate the important development activities we have been focusing on such as ultra thin package profiles, finer line/space widths down to 2μm/2μm and multi-layer redistribution in order to achieve smart system integration at a lower cost for our customers,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.
“This consortium has members from the entire supply chain, and with the combined experience and knowledge of all the members, the solution developed will be industry leading and targeted for high volume manufacturing benefiting the industry as a whole,” said Mr. Cheam Tong Liang, Vice President, Advanced Packaging Business Line & Corporate Strategy of Kulicke & Soffa.