Processing of graphene on 300mm Si wafers in a state-of-the-art CMOS fabrication facility

The building blocks are described that can be used to fabricate other novel device architectures that can take advantage of the unique properties of graphene or other interesting single-layer (i.e., 2D) materials.

BY V. KAUSHIK, N. AGBODO, H. CHUNG, M. HATZISTERGOS, B. JI, P. KHARE, T. LAURSEN, D. LOVELL, A. MESFIN, T. MURRAY, S. NOVAK, H. STAMPER, D. STEINKE, S. VIVEKANAND, T. VO, M. PASSARO AND M. LIEHR, College of Na- noscale Science and Engineering, SUNY Polytechnic Institute, Albany NY.

Graphene is a 2-dimensional sheet of sp2-hybridized carbon atoms with unique physical, mechanical and electrical properties. Commonly found in its multi-layer form, graphite, its isolation as a single-layer has received major attention in the literature for CMOS applications in low-power, high-mobility, analog and radio-frequency devices [1-5]. Single layers of graphene can be obtained by exfoliation from graphite, thermal decomposition on SiC surfaces [6], or chemical vapor deposition (CVD) on metallic surfaces such as copper or nickel. For the evaluation of its compatibility with silicon-based CMOS, it is necessary to study graphene layers on silicon wafers. In this article, we demonstrate the introduction of single-layer graphene — grown by CVD and transferred to 300mm Si wafers — into a state-of-the-art CMOS fab, and the further processing of these wafers using advanced CMOS techniques in order to obtain working graphene-channel FETs. The fabrication steps developed in this work, chosen to minimize impacts to graphene quality during fab-based processing, can serve as building blocks for future research in conventional and novel device architectures.

Graphene growth, etch and transfer

Graphene was grown by low-pressure CVD in a typical tube furnace on commercially available Cu foil at ~950C by CH4 cracking. Prior to graphene transfer, a thermal- release tape was placed on the Cu foil to serve as a support for further processing. The Cu foil was then etched using a mixture of hydrochloric acid, hydrogen peroxide and de-ionized (DI) water. Multiple sequences of this etch were used to minimize re-deposition of the etched copper onto the tape with graphene, followed by a final DI water rinse, leaving only the graphene and tape remaining. The tape and graphene adhesion was then placed on a 300mm Si wafer or a Si wafer capped with SiO2 (SiO2/Si) and heated to remove the tape, resulting in a wafer with graphene on its surface. (Although the use of PMMA [poly methyl acrylate] has been reported [7] as a suitable support film for graphene transfer, we did not use it since the PMMA is typically dissolved in acetone, a solvent that is incompatible with 300mm fab integration due to health and safety considerations.)

Due to the use of Cu foil and laboratory instruments, the graphene growth, etch and transfer processes have the potential to leave residual metal contamination on the wafer. Since the introduction of these wafers into the fab for further processing requires demonstration of low levels of metal contaminants, the handling of the graphene-on-Cu foil and the Cu-etching was performed by avoiding the use of metallic instruments. The detection of metallic ions on the transferred graphene was performed by TXRF (Total-reflection X-Ray Fluorescence), which is a highly surface sensitive technique. Using this feedback, we were able to determine that the use of ceramic scissors for cutting the foil, ceramic tweezers for handling the tape and foil, and a well-ventilated clean laminar-flow hood area were effective in reducing metallic contaminants.

FIGURE 1A shows an optical micrograph of graphene transferred on a SiO2/Si wafer and post-transfer cleans. While graphene covers most of the wafer surface, some gaps were observed due to imperfections in the transfer process. The use of thermal tape can potentially cause tape residue to remain on the graphene as well (shown in Figure 1a), which is partly mitigated by post-transfer cleans.

FIGURE 1B shows TXRF data of the concentration of metallic contaminants after graphene transfer and after post-transfer cleans using HCl chemistry. TXRF spectra of the SiO2/Si wafer after transfer showed high levels of metallic Cu, Fe and Ti. Post-transfer cleans of the wafer reduced the metallic contamination levels to ~5E10 at/ cm2.

Raman spectroscopy is the technique most often used to measure the quality of monolayer graphene [2,8]. High quality graphene shows distinct peaks at 1580cm-1 (G peak) and 2690cm-1 (2D peak). In undamaged graphene the 2D peak is a factor of two higher than the G peak, with this ratio decreasing as the layer accumulates damage. In addition, damaging the graphene causes the appearance of a peak at 1350cm-1 (D peak). These features have been used to monitor the quality of the graphene layers at various stages in our process. FIGURE 1C shows a Raman spectrum of the graphene immediately following the transfer. The intensities of the 2D- and G-peaks are consistent with those for single-layer graphene. The low intensity of the D-peak in FIGURE 1D confirms that wet clean sequences used did not significantly degrade the electrical and physical properties of the graphene.

Graphene 1-A Graphene 1-B Graphene 1-CGraphene 1-D replace

FIGURE 1. Shown is an optical micrograph of the graphene after transfer on to a SiO2/Si wafer and cleans indicating areas with graphene (A), areas with no graphene ((B) and suspected tape residue (C).Figure 1b shows metal contamination levels determined from TXRF spectra for as-transfer and after wet cleans. Figure 1c and d show Raman spectra obtained from graphene on SiO2 wafer before and after wet- cleans respectively showing no degradation in single-layer graphene quality.

Device fabrication: Gate and dielectric formation

A simple MOSFET-like integration scheme using graphene as the channel material was chosen to demonstrate the processing of graphene in our 300mm line. For best device performance, a high quality gate dielectric is required, and several dielectric layers deposited over graphene were evaluated using Raman spectroscopy to observe their effects on graphene quality. Processes that involved high temperatures — e.g., CVD or plasmas — introduced defects into the graphene, as is evident from a D-peaks shown in FIGURES 2A and 2B, thus ruling out typical gate dielectric layers available in CMOS fabs. Atomic layer deposition (ALD) processes have been reported to show poor nucleation on the graphene surface due to a lack of available bonds [9]. Evaporation processes, reported to be effective after depositing a thin metal on top of the graphene which is then oxidized, are not well suited to modern high volume manufacturing fabs. To circumvent these problems, we ‘inverted’ the conventional MOSFET structure using buried gates [10]. In this scheme, tungsten gate electrodes were fabricated in thermal oxide by a damascene process. After these electrodes were in place, a gate-quality 4nm HfO2 dielectric was deposited using an ALD process. Graphene was then transferred onto this HfO2 surface. This approach eliminates the need for a gate-quality dielectric deposition over the graphene. FIGURE 3A shows the process sequence for the device while FIGURE 3B shows a schematic of the device structure.

Graphene 2-A Graphene 2-B Graphene 2-C Graphene 2-D


FIGURE 2. Shown are Raman spectra of the graphene layer with D-peak indicative of damage after after a) plasma oxidation and b) PVD metal deposition and oxidation. Figures 2c-d show Raman spectra after c) spin-on dielectric deposition and d) after subsequent bake anneal indicating a reduction 2D/G peak ratio but no D-peak.

In order to process the wafers after graphene transfer, we capped the graphene with a spin-on dielectric film to protect its quality. We were thus able to avoid the above mentioned issues of high temperature, plasma processing, and nucleation. The spin-on dielectric film was ~35nm thick and allowed the graphene layer to withstand higher temperature and plasma processes, including film depositions, anneals, and reactive ion etching (RIE). With no discernible D-peak, the Raman spectra in FIGURES 2C AND 2D show that the capping layer preserved graphene quality.

Figure 3a: Schematic of process steps used in the fabrication of graphene-channel devices.

Figure 3a: Schematic of process steps used in the fabrication of graphene-channel devices.

Graphene 3-B

FIGURE 3B. Schematic of device structure to exercise process steps.

Subsequently, a photolithography step followed by an RIE process was used to pattern the active area and to remove the capping dielectric, graphene, and gate oxide from the field area (FIGURE 4A). With the active graphene area patterned, the process then moved to the contact module.

Device fabrication: Contact formation

The formation of metal contacts to graphene is one of the more challenging aspects of fabricating a graphene device in a modern fab. Most of the available literature reports the use of e-beam evaporation and lift-off techniques to form metal contacts to graphene [11,12]. However, these techniques and the typical metals used (Au, Au-Pd, Cr) are more suited to a lab environment than a high-volume Si fab. We used a conventional damascene contact process and a plated Cu-based metallurgy, which introduced challenges associated with the contact open etch and cleans, and during metal depositions.

In this study, the contact stack consisted of conventional nitride and oxide that was planarized using chemical-mechanical polishing (CMP). Immersion lithography was used to define contacts with dimensions ranging from 100nm to 350nm. After the dry etch process, the wafers were cleaned using a wet chemistry compatible with the exposed graphene. A modified metal barrier/liner/seed process was then used to initiate the metallization process in the contacts, followed by CMP of the metal overburden. Contact to the graphene was made along the circumference of the contact plug, which has been reported to be more effective than top contact schemes [13]. The contact module was followed by a standard metallization module using a damascene copper process to fabricate the pads for automated in-line testing of the graphene FETs. Future work will include further optimization of etches and variations of liner metallurgy and contact architecture (top vs. edge) to study the effects on contact resistance and device performance.

Electrical test results

The devices were tested using DC current-voltage sweeps on various graphene-channel MOSFETs (GFETs) using a standard parametric tester. Two-point transport measurements demonstrated the MOSFETs’ gate-voltage-induced resistance modulations. A typical transport curve is shown in FIGURE 4D. Transistor behavior was observed in GFET devices with various graphene channel widths ranging from 1μm to 10μm. GFET channel widths ranging from 50nm to 10μm were controlled by the patterned back gates. Low operating voltages (with Vg swept from -1V to 1V) were achieved due to our utilization of a thin high-k dielectric. The Dirac point in FIGURE 4D is shown to be nominally at 0V with the gate resolution at 50mV, which is the step-size of the sweep. Since we only used 2-point testing, the measured total resistance includes the channel resistance, series resistance of graphene area not covered by the gate, and the graphene-metal contact resistance. While this limits our ability to characterize the intrinsic GFET transport property, it does point to the challenges for the fabrications of product-like devices; i.e., significant reductions of contact and series resistances are definitely required.

Graphene 4-A Graphene 4-B Graphene 4-C Graphene 4-D


FIGURE 4:  4a shows XSEM of metal gate and active region after pattern and etch. Figure 4b shows lower magnification view of copper contacts through insulator and metal at top. Figure 4c shows higher magnification view of 100nm contact. Dotted line shows expected location of graphene. Figure 4d shows a transport curve of graphene FETs using a 2-point transport measurement on an in-line parametric tester. The gate voltage is controlled by the patterned back gate. The total resistance includes the channel resistance, series resistance of graphene area that is not covered by the gate, and the graphene-metal contact resistance. 


We have demonstrated that working MOSFETs with graphene channels can be fabricated in a conventional 300mm CMOS fabrication line using state-of-the-art process tools. The building blocks shown here can be used to fabricate other novel device architectures that can take advantage of the unique properties of graphene or other interesting single-layer (i.e., 2D) materials. Further optimization of graphene transfer and contact schemes intended to reduce overall resistance are ongoing and will be reported in subsequent publications.


The authors acknowledge the support of Profs. Alain Diebold and Ji-Ung Lee.


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The authors are with the College of Nanoscale Science and Engineering, SUNY Polytechnic Institute, 257 Fuller Rd, Albany NY 12203. 


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