Controlling warpage in advanced packaging

BY DR. PHIL GARROU, Contributing Editor

As we continue to miniaturize, warpage remains the main problem encountered in all areas of advanced packaging. At ECTC, Kotake of Hitachi Chemical addressed “Ultra low CTE core materials for next generation thin CSPs.” They describe ultra low CTE (1.8) core materials (E-770G) which are used to reduce warpage in PoP packages. Hitachi simulations show that the CTE of core materials has more impact that the modulus. Best results are obtained when using the new material E-770G for both core and prepreg. Kim and co-workers at Amkor reported on “Strip grinding Introduction for thin PoP.” Typical PoP used in mobile products consists of a logic function In the bottom package and a memory function in the top package. The most difficult barrier to fabricate the thin PoP is warpage control. Amkor TMV (through mold via) PoP structures can be overmolded or exposed die (to allow for heat sinking). When trying to thin the package, there is a limit to the thinness of the overmold and a limit to the silicon die thickness since thinner die result in die chipping or cracking during handling. In the thin mold cap case, it’s not easy to control the package warpage. The warpage can be controlled with a thicker substrate, but this increases the package thickness.

The concept of strip grinding is to grind the mold compound and die together. The advantage of strip grinding is to use normal die thickness and mold cap thickness, thus reducing the risk of thin die handling and narrow mold clearance. Mold flash is eliminated through the grinding methodology. By applying a strip grinding process, a very thin die and mold cap can be easily generated.

Double side molded structures are possible, which help make a balanced structure on top and bottom which tends to improve the warpage performance. Bottom side mold is difficult, because the BGA ball is mounted on the bottom area.

For the double-sided mold process flow, chip attach on the top side and BGA ball attach on the bottom side need to be done first followed by double side mold. The bottom molding is ground until the bottom ball is exposed. To remake a BGA, a second ball attach needs to be performed to generate a proper BGA standoff.

Bchir of Qualcomm discussed “improvement of substrate and package warpage by copper plating optimization.” While substrate warpage is typically approached through modification of dielectric material properties (such as CTE, Tg, modulus), layer thicknesses (core, prepreg, solder resist and Cu thickness), and Cu areal density per layer there is also an impact from the Cu plating process. Electroplated Cu thin films have porous grain boundaries, wherein grain boundary volume is strongly dependent on electroplating condi- tions and subsequent thermal processing. During thermal processing, Cu grains grow and merge, elimi- nating grain boundaries and causing shrinkage. The residual stress in the initial deposit, coupled with shrinkage during subsequent thermal processing, strongly impacts the warpage of the substrate and package. This is compounded by the inherent front-to- back Cu density imbalance which is typical in substrate design.

Choice of electrolytic Cu plating solution has significant impact on the magnitude of package warpage. The influence of Cu plating solution on warpage is related to the resulting grain size distribution and stress state deposited from a given chemistry. Plating additives can be co-deposited as impurities into the Cu layer, and have been shown to strongly impact residual stress and grain coarsening behavior of the Cu deposit.

They found that reducing the plating current density for a given plating solution led to substantial reduction in package warpage. Also, an increase in the plating current density causes a reduction in the deposited grain size, hence a reduction in current density would lead to larger deposited grains and thus larger grains would mean reduced grain boundary volume, less “shrink” in the Cu layer and lower residual stress in the Cu.

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