Rebirth of mask process correction for better wafer lithography

Steffen Schulze is the director of Marketing, mask Data Preparation and Platform Applications at Mentor Graphics, serving customers in mask and IC manufacturing.

Who knew that mask process correction (MPC) would again become necessary for the manufacturing of deep ultraviolet (DUV) photomasks? MPC can be called a seasoned technology; it has always been an integral part of the e-beam mask writers to cope with the e-beam proximity effects, which can extend up to 15um of the exposure point. In addition, the mask house has been compensating for process-induced biases. Residual errors were always absorbed by the models created to describe the wafer process. Range and general behavior proved to be sufficient to capture the effects and secure the accuracy requirements for the wafer lithography.

At the 40nm node, more complex techniques were considered to cope with significant proximity signatures induced by the dry etch process and the realization that forward scattering in e-beam exposure, which was not accounted for in the machine-based correction, had a significant impact especially in 2D configurations. A number of commercial tools were made available at the time but a broad adoption was thwarted by the introduction of new mask substrates and the associated etch process – OMOG blanks provided for a thinner masking layer and enabled an etch process with a fairly flat signature. The MPC suppliers moved on to the EUV technology domain where a new and thicker substrate with a more complex etch process showed stronger signatures again, along with new effects of different ranges.

So what is changing now? At the 10nm node we are still dependent on the 193nm lithography. And while the wafer resolution is tackled with pitch splitting, the accuracy requirements continue to get tighter – tolerances far below 1nm are required for the wafer model. Phase shift masks are considered with a stack that is higher and displays stronger signatures again. In addition, scatter bars of varying sizes but below 100nm at the mask fall again into the size range with significant linearity effects.

So no wonder that the mask and wafer lithography communities are turning to mask process correction technology again. Wafer models have expanded to a more comprehensive description of the 3D nature of the mask (stack height and width ratio are approaching 1). A recent study presented at SPIE (Sturtevant, et al http://dx.doi.org/10.1117/12.2013748) shows that systematic errors on the mask contribute more than 0.5nm RMS to the error budget.  Figure 1 shows the process biases present in an uncorrected mask for various feature types – dense and isolated lines and spaces. Figure 2 shows how strongly the variability in mask parameters – here stack slope and corner rounding – can influence the model accuracy for a matching wafer model.

Figure 1 copy
Figure 1. Mask CD bias (actual-target) 4X for four different pattern types and both horizontal and vertical orientations. Click to view full screen.
Figure 2 copy
Figure 2 .  Impact of changing the MoSi slope (left) and corner rounding (right) on CTR RMS error at nominal condition and through focus. Click to view full screen.

The authors showed that the proper representation of the mask to a wafer model can improve the modeling accuracy significantly. For example, even an approximation of the corner rounding by a 45deg bevel can have a significant impact. Likewise considering the residual linearity and proximity errors improves the modeling accuracy. Figure 3 shows the comparison of residual errors for a variety of test structure in the uncorrected stage and when simulated with the proper mask model. The latter one can largely compensate the observed errors.

Figure 3. Mask CD error (4X) versus target and residual mask process simulation error. Click to view full screen.

The methods to properly account for the effects during the simulation are anchored in mask processing technology. These results have opened the discussion as to not only describing the mask but also correcting it. The above mentioned study revealed a number of additional parameters that are generally assumed to be stable but fundamentally reveal a high sensitivity of the lithomodel to any variation –specifically the material properties and the edge slope or a substrate over-etch.  From these studies and observations one can conclude that mask process characterization and correction will be of increasing importance for meeting the tolerance requirements for wafer modeling and processing – initially by proper description of its residual errors for consideration in the wafer model but subsequently also by correction. The technology is available for quite some time and ready to be used – unless the materials and the process community come through again.

Read other Mentor Graphics blog posts:

Innovations in computational lithography for 20nm

Looking for an integrated tape-out flow

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