Mohith Verghese, ASM America, Phoenix, AZ USA; Mauro Alessandri, Numonyx, Agrate Brianza, Italy
Technological innovations in superior cell architectures, new materials, and advanced deposition techniques such as atomic layer deposition (ALD) will be required to enable the continued growth in flash memory. As a result, technology development efforts in the flash memory market parallel leading research in logic transistor development, such as the use of high-k dielectrics and work function engineered metal gates. Furthermore, novel memory architectures utilizing phase change materials and ferroelectric thin films are being investigated to respond to the mounting scaling challenges of non-volatile memory (NVM) cells.
Flash memory is the fastest growing IC market in history, fueled by new applications in multimedia data storage and mobile consumer products requiring robust, inexpensive data capacity in a smaller form factor. Flash is a specific type of non-volatile (NVM) read-only memory — memory that does not require power to maintain the information stored inside the chip — that is erased and programmed in large blocks. Flash accounted for 8% of the total $277 billion semiconductor industry in 2008, and is expected to post higher than average growth rates of 18% annually . The demand for memory capacity has resulted in aggressive scaling of flash memory cells far in excess of projections by the International Technology Roadmap for Semiconductors (ITRS). The exponential growth in density and performance of flash memory cells requires reliable low power/voltage operation, fast erase/write characteristics, improved memory retention, and increased endurance while cell dimensions are scaled repeatedly at each successive node. Revolutionary advances in lithography techniques continue to facilitate the shrinking of cell areas. However, aggressive density scaling results in formidable challenges that are encountered as flash memory program/erase voltages become incompatible with scaled low voltage devices. To address these challenges, ALD of high-k dielectrics and novel metal layers are being developed to tackle many of the issues related to speed, endurance, and reliability of flash memory cells.
New materials and deposition technologies address scaling
In conventional floating gate memory, aggressive density scaling gives rise to several issues. The voltage transfer from the control gate to the floating gate is defined by the following relationship:
Vfg = CR*Vcg
Vfg is the floating gate voltage, Vcg is the control gate voltage and CR is the coupling ratio. The coupling ratio is the ratio of the floating gate capacitance and the total capacitance.
CR = Cipd / (Cipd + Cto)
Cipd is the capacitance of the inter-poly dielectric (IPD) and Cto is the capacitance of the tunnel oxide. As a result of array densification, floating gate memory cells can start to lose sidewall capacitance area leading to loss of IPD capacitance (Figure 1). This is already true at the 45nm node, where the distance between two adjacent memory cells is not much more than twice the thickness of the IPD layer. Standard ONO IPD layers are not feasible below 10-12nm equivalent oxide thicknesses (EOTs), due to major issues related to the charge retention properties of the cell . Replacing the ONO layer with a high-k dielectric results in a marked improvement in capacitance and allows further scaling of IPD EOTs. This in turn results in better coupling of control gate and floating gate voltages, allowing program/erase voltages to be further reduced to satisfy the requirements of next-generation low-power devices.
Figure 1. Densification of flash cells requires new materials and deposition techniques. (Source: ASM)
Charge trap devices also benefit from the use of high-k materials. One of the main issues with charge trap memory is the unwanted injection of charge from the control gate, through the blocking oxide, into the charge storage layer. Program/erase speed for charge trap memory is determined by competition of direct band-to-band tunneling through the thin tunnel oxide and FN tunneling through the blocking oxide . Hence, extremely thin tunnel oxides are required to maximize the ratio of hole transfer (through tunnel oxide) to electron transfer (through blocking oxide) for stable erase operations. However, thin tunnel oxides can lead to considerable charge loss over time via back tunnelling, affecting the retention quality of the memory. It has been shown that the use of high-k materials such as aluminum oxide for the blocking oxide can reduce the electric field across the blocking oxide while increasing the electric field across the tunnel oxide . Therefore, thicker tunnel oxides can be used to improve retention without losing erase speed. Furthermore, the lower electric field across the blocking oxide reduces the amount of parasitic injection of charge from the control gate.
Erase saturation is also a problem in charge trap memory. This phenomenon is characterized by the saturation of erase VT level as the erase voltage is increased. During the erase operation, holes are injected from the substrate into the nitride trap layer. However, electrons are also injected from the control gate through the blocking oxide. The injected charges increase the field across the blocking oxide, enhancing the electron injection from the gate. Hence, the erase VT saturates at high erase voltages. To avoid this, a high-workfunction, p+ polysilicon gate electrode can be used . However, when using a high-k dielectric as a blocking layer, a high-workfunction metal control gate is preferred due to the known incompatibilities between polysilicon and high-k dielectrics (intermixing, Fermi level pinning, etc.). Tantalum nitride based metal electrodes have been shown to substantially improve erase saturation behavior in charge trap memories .
Atomic layer deposition (ALD) of both dielectrics and metals is the leading deposition technique of choice for next-generation flash memories. The ALD process has intrinsic advantages over traditional deposition processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). Capitalizing on surface saturation reactions, ALD processes have inherent thickness control and are highly stable, being insensitive to fluctuations in both temperature and reactant flux. The resulting films are pure, dense, smooth and highly conformal, attaining perfect step-coverage on feature aspect ratios as high as 100:1. As shown in Fig. 1, aspect ratios in highly dense memory cell arrays are becoming much more challenging. The ALD process is best suited to attaining perfect step coverage for high-k IPD/blocking oxide layers, control gate metals, and shallow trench isolation (STI) oxides. Furthermore, the ALD technique is most likely to result in stoichiometric, pure films with low trap densities. This is especially important for IPD/blocking and tunnel oxides, where trap assisted tunneling of charge can lead to poor memory retention qualities.
Figure 2. Leakage characteristics of different blocking layers. (Source: ASM)
Material requirements for high-k and metal gate films in flash memory are different from those in logic circuits. Scalability and interfacial layer formation is not as critical in memory, and dielectric constants on the order of 10-20 are suitable . However, dielectrics used in memory IPD and blocking layers need to demonstrate much more stringent leakage performance (<1E-13A/cm2 @ 4MV/cm) because of long retention requirements. Materials also need to be thermally stable through high-temperature anneals and must be compatible with thermal oxidation chemistries that are commonplace in the flash memory process flow. To date, aluminum oxide deposited by ALD has been shown to be most promising as a high-k dielectric for IPD and blocking layers (Figure 2). The large band gap and low bulk trap density of aluminum oxide films leads to excellent retention properties. However, the relatively low k value of aluminum oxide limits the scaling potential of this material. Higher-k alternatives such as hafnium oxide are actively being investigated but options are typically severely limited due to intrinsically lower band gaps and higher trap densities leading to very poor retention characteristics.
Controlled mixing of higher-k materials with aluminum oxide is a potential pathway to obtaining the ideal layer with good retention and program/erase characteristics. Oxides of lanthanum and other heavy rare earths (RE) are promising high-k materials that may be suitable for blocking oxides when mixed with aluminum oxide. The rare earth oxides have high k values (>20) and relatively large band gaps. ALD deposition techniques can be used to finely tune the stoichiometry of the mixed film. This is done by varying the pulse ratio of one precursor to the other. Composition of lanthanum aluminate ALD films can be varied from lanthanum rich to aluminum rich by changing the pulse ratio; aluminum oxide doped with lanthanum oxide can improve program/erase performance (Figure 3).
Figure 3. Stoichiometric control of lanthanum aluminate films by ALD. (Source: ASM)
Although flash memory is by far the most dominant non-volatile memory today, several alternative technologies can potentially provide faster programming times, lower programming voltages and increased endurance. The polarization state of a ferroelectric capacitor can be switched and sensed in ferroelectric random access memory (FeRAM). Ferroelectric materials have more than one stable state for a charged ion in the unit cell of the lattice structure. Application of an external electric field can shift the position of a charged ion, resulting in electrostatic polarization. A hysteresis curve of a ferroelectric capacitor (Figure 4) shows the polarization response to an externally applied electric field. Theoretically, ferroelectric polarization can occur in <1nsec, but actual switching times of the memory cell can depend on the time constants of the peripheral circuitry . Switching times on the order of 10-20nsec have been demonstrated.
Figure 4. ALD of diffusion barrier protects ferroelectric layer and maintains hysteresis in polarization curve. (Source: ASM)
Common ferroelectric materials include lead-zirconium-titanate (PZT), strontium-bismuth-tantalate (SBT), and strontium-bismuth-niobiate (SBN). All these materials are sensitive to hydrogen exposure and ALD of protective barrier material is becoming a common process step to protect the ferroelectric layer from hydrogen rich semiconductor processes in subsequent manufacturing steps. ALD has been chosen as the most appropriate deposition technique due to characteristics such as low thermal budget processing, near perfect step coverage and pin-hole free layers. Ferroelectric memories have phenomenal growth potential and ALD layers can enable their insertion into the mainstream.
Chalcogenide-based phase change memory (PCM) is another alternative novel memory being actively investigated. A chalcogenide is a unique material that can rapidly change from amorphous to crystalline phase with the application or removal of heat. Differences in electrical resistivity between the two phases can be utilized to store data in a PCM memory cell. The basic phase change material is a germanium-antimony-tellurium (GST) alloy. Current is passed through a heater element to cause local joule heating to change the crystallinity of the PCM material in contact with the heater. Phase change can occur on the order of 10nsec and the material can be cycled between 109 and 1013 times — considerably in excess of the 106 write/erase cycles required by modern day flash technologies . Besides speed, endurance and low voltage operation, PCM memory is highly scalable. Because PCM memory uses a deposited thin-film structure that is not inherently tied to the silicon substrate, there is potential to stack these memory arrays on back-end metallization layers, resulting in higher densities. Denser arrays and the need for low thermal budgets and high conformality have resulted in active study of ALD techniques for the deposition of GST, resistive heater metal layers and post-GST dielectrics.
Non-volatile memory (NVM) is a dominant semiconductor device market with immense growth potential and flash memory represents a considerable fraction of modern day NVMs. Geometry scaling of flash memory is reaching fundamental limits and continued scaling of flash memory will require insertion of new materials and deposition technologies into the standard NVM process flow. Next-generation memory technologies will also require radical new materials and thin film deposition techniques. ALD of high-k dielectrics and novel metal layers will be prevalent in producing next-generation NVMs because it has been shown to address many of the issues related to speed, endurance, and reliability of these devices.
- 2008 Flash Memory Report, Research Report #DB1185, Databeans Research Group, October 2008.
- M. Alessandri, R. Piagge, S. Alberici, E. Bellandi, M. Caniatti, G. Ghindini, et al., “High-k Materials in Flash Memories,” ECS Transactions, Vol. 1, No. 5, pp. 91-105, 2006.
- J. Bu, M. White, “Design Considerations in Scaled SONOS Nonvolatile Memory Devices,” Solid State Electronics, Vol. 45, pp. 113-120, 2001.
- C. Lee, S. Hur, Y. Shin, J. Choi, D. Park, K. Kim, “Charge-trapping Device Structure of SiO2/SiN/High-k Dielectric Al2O3 for High-density Flash Memory,” Applied Physics Letters, Vol. 86, 152908, April 2005.
- H. Bachhofer et. al., Journal of Applied Physics, Vol. 89, p 2791, 2001.
- C. Lee, K. Choi, M. Co, Y. Song, K. Park, K. Kim, “A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN Metal Gate for Multi-giga Bit Flash Memories,” International Electron Devices Meeting, Vol. 3, p613, 2003.
- G. Derbenwick, A. Isaacson, “Ferroelectric Memory: On the Brink of Breaking Through,” IEEE Circuits and Devices, January 2001.
- S. Hudgens, B. Johnson, “Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology,” MRS Bulletin, November 2004.
Mohith Verghese received his BS from the U. of Texas at Austin and his MS from the U. of Arizona, both in chemical engineering. He is a technical product manager at ASM America, 3440 East University Drive, Phoenix, AZ 85034, USA; ph.: +1 602 470-2736; E-mail: [email protected].
Mauro Alessandri received a degree in physics from the U. of Milan in 1982. He is the advanced FEOL R&D director at Numonyx, Via C. Olivetti 2, 20041 Agrate Brianza, Milan, Italy.