Process Watch: Taming the overlay beast

Overlay error is the offset in alignment between pattern at one step of a semiconductor process and pattern at the next step. Traditionally overlay error has referred to successive device layers, but in the case of double-patterning lithography, overlay error may stem from interwoven patterns at the same layer. Regardless, controlling overlay error is one of the most difficult issues that lithography engineers face in this era of shrinking design rules and complex, advanced lithography techniques. Because overlay error can affect yield, device performance and reliability, it must be measured precisely, and all sources of systematic overlay error must be discovered and addressed. These may include mask pattern placement error, deviations from wafer planarity, scanner nonlinearities and process variation.

In most cases, overlay error is measured optically by capturing an image of a specially designed alignment mark called an overlay target. Half of the overlay target is printed during the first process step, and the other half of it is printed during the second process step.


A standard overlay target is printed in two steps,  indicated in red and blue, and structured to measure the errors in x and y.

An overlay metrology tool captures the image and quantifies the alignment between the first and second parts of the target. The result is reported as a vector quantity, having a magnitude and direction corresponding to the x and y offsets. The procedure is repeated for each of the overlay targets on the wafer. Overlay error maps are comprised of a circular field of tiny vectors, representing the overlay error across the wafer. These maps are used to adjust the scanner or to uncover issues with the mask pattern, the wafer shape or the process. Overlay error maps are also used to disposition wafers.

Flexible, robust multi-layer target allows simultaneous measurement of overlay error within the same layer and between layers.

A recent development in the area of overlay measurement is extension of measurement capability to new layers and new materials (see above). When overlay error between layers is measured, the optical properties of the top layer are critical to the quality of the data. The metrology tool needs to be able to send photons through the top layer to detect the pattern underneath, and the quality of the image of the buried pattern is critical to the quality of the overall measurement. Because semiconductor processes use a variety of materials, and the optical absorption of a given material generally varies with wavelength, the well-equipped metrology system can select from a variety of wavelengths to achieve sufficient image quality for the buried pattern to enable an accurate, repeatable measurement. The alternative—introducing an extra process step to etch a “window” in the top layer before patterning it—adds significant cycle time and may degrade the underlying pattern. Cycle time pressures are ever-present and well known. Furthermore, when the entire overlay error budget is limited to a small number of nanometers, lithographers cannot afford to allot a large portion of the budget to uncertainty in the output of the overlay metrology tool.

Examples of particularly challenging classes of materials are those used to build 3D transistors, and hard mask materials used during litho-etch-litho-etch lithography. Hard mask materials are opaque to visible light, and their optical properties may fluctuate with composition and even with annealing temperature.  The latest overlay metrology systems can provide an appropriate wavelength that penetrates the top layer, making overlay metrology feasible without additional process steps.

Another new development in the field of overlay metrology is the use of multi-layer overlay targets. New target designs now allow a lithography engineer to measure within-layer overlay and between-layer overlay using one target. These innovative targets are small enough to be inserted into the die without consuming an unfeasible amount of valuable real estate. Their designs are flexible and robust, allowing adjustments for specific process and layer requirements. They are compatible with various pitch-splitting and double-patterning schemes. Most importantly, the new multi-layer targets allow lithographers to measure within- and between-layer overlay error with one image and, at the same time, reduce systematic errors that could degrade the measurement if separate targets had been used.

Overlay metrology remains one of the most challenging issues that lithographers currently face. Innovations in overlay metrology tool and target design must continue, to enable our industry to make smaller, faster, lower power, more affordable chips.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Amir Widmann is a senior director in the Optical Metrology division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”


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