Soitec's extreme SOI: Scalable below 14nm


August 10, 2011 - Post-22nm and below, the industry is going to fully depleted structures, either FinFETs or fully-depleted planar SOI (FDSOI), explained Steve Longoria, SVP, global strategic business development at Soitec, in an interview at SEMICON West 2011. Although Soitec supplies wafers for both structures, the company has introduced a new wafer -- extreme SOI -- with a thin buried oxide that is used for planar FDSOI. According to an IC Knowledge paper cited by Longoria during the interview, the new technology delivers superior power performance and is cost-competitive with bulk technology. All the major fabless companies and foundries have initiated programs to evaluate the technology, he noted, which Soitec believes is an alternative for 22nm and below.

In a partnership with IBM and ARM, the company was able to demonstrate two different variants: a 30% performance advantage at the same voltage, or a 40% power savings at the same performance. The company leveraged its Smart Cut technology to build the thin buried oxide, and is working with its partners to develop the transistor on top of it. According to Longoria, the development is straightforward because it's a continuation of a planar transistor. "So it's evolutionary and straightforward from both a process design standpoint and a manufacturing standpoint," he said. "It's a much lower risk in the industry for both the designer and the manufacturers than the alternatives."

The company is producing prototypes of extreme SOI now, and providing manufacturing samples on the order of thousands of wafers a month to all the development facilities. "We are in position [between the company's factories in Singapore and France] to be fully qualified by the end of this year, and our close partnership with SEH in Japan will enable millions of wafers to be supplied over the next couple years," reported Longoria. He said the company is well positioned to meet both the quality and specifications and the volume manufacturing with FDSOI or extreme SOI going forward. "Research suggests we can thin the buried oxide down even more and have scalability well below 14nm, maybe even 11nm -- enabling scaling of a planar device, which is going to put the industry in a position to move even faster."

Font Sizes:


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. 


Electroiq 2 EIQ2


Automated Test Creation for Mixed Signal IP using IJTAG

The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embe...

Faster Time to Root Cause with Diagnosis-Driven Yield Analysis

This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent® Diagnosis and Tessent YieldInsight® software...


Innovation in Semiconductor Manufacturing Instrumentation

As the industry is incorporating more MEMS devices with integrated magnetic sensors, they are encountering challenges that cannot be overcome with ...

3D and 2.5D Integration: A Status Report Live Event

This webcast will explore the present status of 2.5 and 3D integration, including TSV formation.

Questions and answers on FD-SOI

Fri Jan 04 14:56:00 CST 2013

Present your ideas at The ConFab in 2013

Mon Nov 26 09:04:00 CST 2012

The ConFab 2013 countdown begins

Thu Aug 09 16:18:00 CDT 2012

The ConFab: Big data is here

Sun Jun 03 19:19:00 CDT 2012

Oh, snap!: Pics from The ConFab

Sun Jun 03 19:09:00 CDT 2012



Volume 56, Issue 1

Article Archive for Solid State Technology.

© 2013. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS