Roadmapping More than Moore: When the application matters


July 13, 2012 -- SEMICON West, this week in San Francisco, CA, hosted 3 TechXPOT sessions on the International Technology Roadmap for Semiconductors (ITRS, 2012 update. At the back-end technologies session, roadmapping for More than Moore was addressed as both a philosophical and technical matter.

Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano-scaling steal the show

Introducing the back-end-focused working group presentations, Bob Doering, representing the Overall Roadmap Technology Characteristics (ORTC), said that the Roadmap is not just about scaling anymore. Patrick Cogez, presenting More than Moore, picked up this thread, saying that the long-time focus on semiconductor scaling now has a partner, diversification, in More than Moore process technologies. More than Moore -- encompassing advanced wafer-level and 3D packaging, micro electro mechanical systems (MEMS), and related microelectronics technologies -- are harder to roadmap than CMOS technologies. Scaling semiconductor nodes has always offered the combined benefits of faster, cheaper, smaller, lower-power chips (Moore’s Law). Whichever aspect was of importance to the system-level application was inconsequential. Not so with More than Moore. Still, ITRS hopes that applying the methodology of a roadmap to these technologies will effectively organize R&D and innovation in the sectors. In a way, a new roadmapping methodology is emerging, Cogez said. Because More than Moore technologies have to be implemented to solve a system-level need, ITRS is roadmapping with applications in mind. Today, these include automotive, lighting, energy, and healthcare electronics. ITRS is partnering closely with iNEMI, an organization that roadmaps for system-level electronics manufacturing, on this initiative.

Paul Zimmerman (Intel), speaking on interconnect materials, reiterated the idea that traditional scaling is slowing, and can only go so far. This is an opportunity for innovation in new materials, he said, and also for support from the design community. Zimmerman used the example of multilayer graphene to show that the exotic material is not enough in and of itself to continue scaling. Perfect multilayer graphene offers a clear advantage over copper for interconnects. However, even a low percentage of edge defects will drop multilayer graphene’s performance below that of today’s Cu interconnects.

Bill Bottoms, presenting on assembly & packaging, gave an example of More than Moore’s applications-driven adoption with Sony’s new PS Vita. In the Vita, a 5-layer stacked die package includes a mix of 3D interconnect and wire bonding. More than Moore is adopted to address a specific need, and conventional packaging continues. In the same package. Blogger Dick James of Chipworks recently dissected this chip, so check out his detailed analysis here.

In MEMS, sensor fusion is creating a kind of node scaling, said Michael Gaitan. MEMS sensors go from stand-alone devices, to triaxial, to 6 degrees of freedom (DoF), then 9, and now 10 DOF. This pace of integration could be considered scaling, and it is moving more rapidly than ITRS expected, promoting an update in 2012. MEMS are also a technology that is driven by application needs -- ITRS and iNEMI are collaborating on MEMS development for healthcare, addressing questions like what the regulatory environment is for consumer health monitoring devices catering to the “worried well” population.

Read about the front-end ITRS update here.

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