2012 ITRS update: Back-end packaging and MEMS

07/13/2012
ITRS

July 13, 2012 -- At SEMICON West 2012, this week in San Francisco, CA, the working groups of the International Technology Roadmap for Semiconductors (ITRS) held 3 sessions (TechXPOTs) outlining 2012 updates to the roadmap. Check out the updates to the front-end, scaling roadmap working groups here.

The ITRS undergoes major revisions on odd-numbered years. 2012 being an even-numbered year, very little change occurred to the Overall Roadmap Technology Characteristics (ORTC). However, within the working groups, some updates were worth noting.

Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano-scaling steal the show

First, the changes to the ORTC, presented at the TechXPOT by Bob Doering. Of interest were changes focused directly or indirectly on 450mm. ITRS has moved the forecast production start date to 2015-2016. The definition of “production” technology also changed, with ITRS relaxing the former rule that at least 2 companies must be implementing a technology within a few months of each other. With consolidation and specialization in the chipmaking industry, ITRS now accepts a new technology or process as “in production” when possibly only one company is using it for many months.

Introducing the packaging focused working group presentations, Doering said that the Roadmap is not just about scaling anymore. There was so much information on this front, that we’ve posted a second article about the More than Moore roadmap methodology here.

Speaking on assembly & packaging, Bill Bottoms enumerated the 8 key areas of focus for ITRS: single-chip packaging issues (mainly getting costs down), copper wire bonding, heterogeneous integration, 2.5D interposers, 3D packaging, thinning, photonics closer to the transistors, and MEMS packaging concerns. Why is through silicon via (TSV) adoption taking so long, Bottoms is often asked. In reality, he says, the ramp to high-volume adoption is fast for TSV, 6 years as compared to the 30 years it took for flip chip and Cu wire bonding to catch on. This is an exciting time for TSV and 3D packaging, Bottoms said, pointing to the Micron/Intel Hybrid Memory Cube as an example. On the point of thinning, Bottoms emphasized that the roadmap is more concerned with how to handle thinned wafers/die/packages, and less with how to actually perform the thinning.

On the photonics integration question, ITRS still has a lot of “bricks” -- items on the roadmap flagged red to indicate that the industry does not know how to tackle a challenge -- and even more yellows -- areas where the industry is not sure if a technology will work.

Developing the micro electro mechanical systems (MEMS) packaging discussion, Michael Gaitan shared the 2 trends in MEMS: continuous, incremental improvements in manufacturing and sensor fusion. Sensor fusion brings test challenges, as more than one MEMS sensor is operating either on the same die or in the same package. MEMS packaging is of interest to the ITRS working group because packaging is 50-80% of the cost of a MEMS device today. Despite this, the majority of development work over the years has gone to front-end MEMS fab.

Test is irrevocably paired with assembly and packaging, especially when 3D integration is involved. The 2012 ITRS updates for the test & test equipment working group are mainly concerned with 3D test, and adaptive test, reported Roger Barth. 3D device test was created as a chapter of the ITRS group in 2011. In 2013, ITRS will be adding a 3D test table (the visual layout for what processes need work), with the hope of better managing known good die (KGD) going into die stacks, and fault-tolerant devices. It is very easy to lower yields and lose money by scrapping a stacked die device with 2 good die and one bad one bonded together, he noted. Die-to-die interactions in a stack can also affect test results. Test handling changes are in store when testing is performed on a thinned die going into a 3D stack. Wafer prober frequencies are on the list for updates as a result of the KGD question.

Other updates in test? Commodity DRAM is moving to full wafer probing earlier than expected. ITRS made a minor update to prober force information in 2012. 450mm wafer probers are expected in 2017. Wafer-level at-speed testing has moved from a “future” technology to “in use,” according to the working group’s online survey. And image sensor test development is going to join the ITRS in 2013.

The final presenter in the ITRS back-end update session was Jack Pekarik, representing the RF and Analog/Mixed-Signal Technologies (RFAMS). Unfortunately, because this working group is planning some major updates for 2013, they’ve opted to keep nearly all of its 2011 set up intact in 2012. We’ll have to wait a little longer to see some major changes to passive device roadmaps, HVMOS, and more. Pekarik did share that demand is driving ITRS to pull in its InP HEMT, InP HBT, and GaN HEMT roadmap by 1 year.

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