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<description><![CDATA[3d Transistor news and technical articles from Solid State Technology Magazine. Search 3d Transistor latest and archived news and articles]]></description>
<link><![CDATA[http://www.electroiq.com/topics/]]></link>
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<title><![CDATA[A Preview of Semicon West 2013]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/print/volume-56/issue-4/features/business/a-preview-of-semicon-west-2013.html]]></link>
<guid>http://www.electroiq.com/articles/sst/print/volume-56/issue-4/features/business/a-preview-of-semicon-west-2013.html</guid>
<pubDate><![CDATA[Mon, 03 Jun 2013 01:00:00 EDT]]></pubDate>
<description><![CDATA[Semicon West 2013, to be held July 9-11 at the Moscone Center in San Francisco, will feature over 500 exhibitors, 50 hours of conference programs and more than 30,000 industry attendees. DEBRA VOGLER, SEMI, San Jose, CA]]></description>
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<title><![CDATA[Confronting sub-20nm front-end challenges with the “duck and weave”]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2013/04/confronting-sub-20nm-front-end-challenges-with-the-duck-and-weav.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2013/04/confronting-sub-20nm-front-end-challenges-with-the-duck-and-weav.html</guid>
<pubDate><![CDATA[Wed, 24 Apr 2013 10:40:00 EDT]]></pubDate>
<description><![CDATA[Just as a boxer avoids a surprise shot to the head or torso by using a “duck and weave” maneuver, so to must front-end technologists confront the challenges associated with extending optical lithography while planning for EUV lithography’s eventual high-productivity solution.]]></description>
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<title><![CDATA[Critical updates on EUV, 3D transistors and 450mm manufacturing at SEMICON West 2013]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2013/04/critical-updates-on-euv--3d-transistors-and-450mm-manufacturing-.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2013/04/critical-updates-on-euv--3d-transistors-and-450mm-manufacturing-.html</guid>
<pubDate><![CDATA[Tue, 23 Apr 2013 13:28:00 EDT]]></pubDate>
<description><![CDATA[The critical processes and technologies necessary to continue Moore’s Law are currently more uncertain than ever before in the history of advanced semiconductor manufacturing.]]></description>
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<title><![CDATA[ARM and Cadence to partner to implement 64-bit processor on TSMC 16nm FinFET process]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2013/04/arm-and-cadence-to-partner-to-implement-64-bit-processor-on-tsmc.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2013/04/arm-and-cadence-to-partner-to-implement-64-bit-processor-on-tsmc.html</guid>
<pubDate><![CDATA[Thu, 04 Apr 2013 16:41:00 EDT]]></pubDate>
<description><![CDATA[Fulfilling the promise of performance and power scaling at 16nm, ARM and Cadence today announced details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC's 16nm FinFET manufacturing process.]]></description>
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<title><![CDATA[Mentor Graphics User Conference 2013 to feature former TSMC CTO]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2013/03/mentor-graphics-user-conference-2013-to-feature-former-tsmc-cto.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2013/03/mentor-graphics-user-conference-2013-to-feature-former-tsmc-cto.html</guid>
<pubDate><![CDATA[Fri, 15 Mar 2013 12:36:00 EDT]]></pubDate>
<description><![CDATA[Mentor Graphics User Conference 2013 speaker line-up boasts a host of industry bigwigs, including former foundry CTO, Dr. Chenming Hu.  Hu will give the keynote address on April 25 in San Jose, California, addressing the future of FinFET.]]></description>
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<title><![CDATA[European consortia, ASML, supplier network plan for 450mm transition]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2012/10/european-consortia-asml-supplier-network-plan-for-450mm-transition.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2012/10/european-consortia-asml-supplier-network-plan-for-450mm-transition.html</guid>
<pubDate><![CDATA[Thu, 18 Oct 2012 07:00:00 EDT]]></pubDate>
<description><![CDATA[At SEMICON Europa, European government representatives, consortia, and suppliers discussed programs to support and participate in the 450mm wafer-size transition -- including a comprehensive presentation from ASML about its roadmap for 450mm EUV platforms.]]></description>
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<title><![CDATA[Process Watch: Taming the overlay beast]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2012/september/process-watch-taming-the-overlay-beast.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2012/september/process-watch-taming-the-overlay-beast.html</guid>
<pubDate><![CDATA[Tue, 18 Sep 2012 08:06:00 EDT]]></pubDate>
<description><![CDATA[In the fourth installment in a series called Process Watch, the authors discuss overlay registration and new capabilities to align to buried layers. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.]]></description>
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<title><![CDATA[NIST tips "hybrid" metrology method to test chips]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2012/september/nist-tips-hybrid-metrology-method-to-test-chips.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2012/september/nist-tips-hybrid-metrology-method-to-test-chips.html</guid>
<pubDate><![CDATA[Thu, 13 Sep 2012 05:00:00 EDT]]></pubDate>
<description><![CDATA[The National Institute of Standards and Technology (NIST) says it's combined scanning techniques and statistical data to both more precisely and less expensively measure features on a chip -- and two big chip firms are already on board.]]></description>
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<title><![CDATA[Supply chain readiness in an era of accelerated change]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2012/08/supply-chain-readiness-in-an-era-of-accelerated-change.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2012/08/supply-chain-readiness-in-an-era-of-accelerated-change.html</guid>
<pubDate><![CDATA[Fri, 10 Aug 2012 09:57:00 EDT]]></pubDate>
<description><![CDATA[In this SEMI News and Views blog, Karen Savala covers EUV lithography, 450mm wafers, and 3D IC developments, based on her recent presentation at SEMICON West, “Supply Chain Readiness in an Era of Accelerated Change.”]]></description>
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<title><![CDATA[ASM debuts 300mm epitaxy and PEALD/PECVD tools for HV transistor fab]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2012/07/asm-300mm-epitaxy-peald-pecvd-tools-for-20nm-transistor-fab.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2012/07/asm-300mm-epitaxy-peald-pecvd-tools-for-20nm-transistor-fab.html</guid>
<pubDate><![CDATA[Wed, 11 Jul 2012 07:54:00 EDT]]></pubDate>
<description><![CDATA[ASM International (ASMI) launched advanced deposition systems for epitaxy, PEALD and PECVD. The 2 tools enable high-volume 300mm wafer processing for 20nm and smaller nodes and 3D transistors.]]></description>
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