<?xml version="1.0" encoding="UTF-8"?>
<rss version="2.0">
<channel>
<title><![CDATA[RSS for Cmos Transistors]]></title>
<description><![CDATA[Cmos Transistors news and technical articles from Solid State Technology Magazine. Search Cmos Transistors latest and archived news and articles]]></description>
<link><![CDATA[http://www.electroiq.com/topics/]]></link>
<atom:link xmlns:atom="http://www.w3.org/2005/Atom" type="application/rss+xml" rel="self" href="http://www.electroiq.com/topics/urss?pageid=488210"/>
<item>
<title><![CDATA[Insights into low frequency noise in high-mobility transistors]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/print/volume-56/issue-2/features/reliability/insights-into-low-frequency-noise-in-high-mobility.html]]></link>
<guid>http://www.electroiq.com/articles/sst/print/volume-56/issue-2/features/reliability/insights-into-low-frequency-noise-in-high-mobility.html</guid>
<pubDate><![CDATA[Fri, 01 Mar 2013 01:00:00 EST]]></pubDate>
<description><![CDATA[The impact of high-mobility channel materials and novel device architectures on the low-frequency noise behavior of 22nm and below CMOS transistors is reviewed. EDDY SIMOEN, imec, Leuven, Belgium]]></description>
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<title><![CDATA[IEDM unveils 2012 program highlights]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2012/september/iedm-unveils-2012-program-highlights.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2012/september/iedm-unveils-2012-program-highlights.html</guid>
<pubDate><![CDATA[Mon, 17 Sep 2012 13:41:00 EDT]]></pubDate>
<description><![CDATA[The 58th annual IEDM will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.]]></description>
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<title><![CDATA[Semiconductor metrology beyond 22nm: Defect inspection and review]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2012/02/semiconductor-metrology-beyond-22nm-defect-inspection-and-review.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2012/02/semiconductor-metrology-beyond-22nm-defect-inspection-and-review.html</guid>
<pubDate><![CDATA[Thu, 23 Feb 2012 15:10:00 EST]]></pubDate>
<description><![CDATA[As semis are manufactured at the 2X and 1Xnm nodes, new metrology technologies must evolve to fill the gaps. In Part 3 of this 3-part metrology series, SEMATECH discusses the inspection/metrology options for advanced semiconductors.]]></description>
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<title><![CDATA[Semiconductor metrology beyond 22nm: 3D memory metrology]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2012/02/semiconductor-metrology-beyond-22nm-3d-memory-metrology.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2012/02/semiconductor-metrology-beyond-22nm-3d-memory-metrology.html</guid>
<pubDate><![CDATA[Thu, 16 Feb 2012 11:37:00 EST]]></pubDate>
<description><![CDATA[The 22nm node marks the beginning of a major transition from conventional scaling of planar memory devices to complex 3D architectures. SEMATECH authors examine the metrology needs of 3D memory device architectures in Part 2 of this three-part series.]]></description>
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<title><![CDATA[Semiconductor metrology beyond 22nm: FinFET metrology]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2012/02/semiconductor-metrology-beyond-22nm-finfet-metrology.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2012/02/semiconductor-metrology-beyond-22nm-finfet-metrology.html</guid>
<pubDate><![CDATA[Thu, 09 Feb 2012 15:33:00 EST]]></pubDate>
<description><![CDATA[SEMATECH authors discuss semiconductor metrology solutions currently being investigated to address the challenges of future nodes. FinFETs raise new metrology complexities, as the entire 3D structure becomes critical for process control, including fin and gate dimensions, profiles and roughness, ...]]></description>
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<title><![CDATA[New architectures, litho schemes take the stage at SEMICON West]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2011/06/new-architectures-litho-schemes-take-the-stage-at-semicon-west.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2011/06/new-architectures-litho-schemes-take-the-stage-at-semicon-west.html</guid>
<pubDate><![CDATA[Fri, 24 Jun 2011 11:07:00 EDT]]></pubDate>
<description><![CDATA[Two TechXPOT sessions at SEMICON West will address the new architectures needed to continue scaling both logic and memory devices, as well as the major challenges facing lithography both for EUV and options for extending 193nm immersion.]]></description>
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<title><![CDATA[Imec: FinFET beat planar for bigger SRAMs]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2011/06/imec-finfet-beat-planar-for-bigger-srams.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2011/06/imec-finfet-beat-planar-for-bigger-srams.html</guid>
<pubDate><![CDATA[Fri, 17 Jun 2011 13:13:00 EDT]]></pubDate>
<description><![CDATA[Planar CMOS slightly outperforms FinFETs for single SRAM cells, but FinFETs  "clearly outperform" and "are superior to planar" for bigger (>128KB) SRAMs, according to new research from imec.]]></description>
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<title><![CDATA[Leveraging ion implant process characteristics to facilitate 22nm devices]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2011/03/leveraging-ion-implant-process-characteristics-to-facilitate.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2011/03/leveraging-ion-implant-process-characteristics-to-facilitate.html</guid>
<pubDate><![CDATA[Tue, 01 Mar 2011 01:00:00 EST]]></pubDate>
<description><![CDATA[Using implant as a precision material modification in contrast to its traditional role as a semiconductor dopant tool, provides enabling technology and new applications. James L. Kawski, Varian Semiconductor Equipment Associates, Gloucester, MA USA]]></description>
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<item>
<title><![CDATA[Leveraging ion implant process characteristics to facilitate 22nm devices]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/print/volume-54/issue-3/features/cover-article/leveraging-ion-implant-process-characteristics-to-facilitate.html]]></link>
<guid>http://www.electroiq.com/articles/sst/print/volume-54/issue-3/features/cover-article/leveraging-ion-implant-process-characteristics-to-facilitate.html</guid>
<pubDate><![CDATA[Tue, 01 Mar 2011 01:00:00 EST]]></pubDate>
<description><![CDATA[Using implant as a precision material modification in contrast to its traditional role as a semiconductor dopant tool, provides enabling technology and new applications. James L. Kawski, Varian Semiconductor Equipment Associates, Gloucester, MA USA]]></description>
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<title><![CDATA[High-k semiconductor materials from a chemical manufacturer perspective]]></title>
<link><![CDATA[http://www.electroiq.com/articles/sst/2011/02/high-k-semiconductor-materials-from-a-chemical-manufacturer-pers.html]]></link>
<guid>http://www.electroiq.com/articles/sst/2011/02/high-k-semiconductor-materials-from-a-chemical-manufacturer-pers.html</guid>
<pubDate><![CDATA[Mon, 28 Feb 2011 09:15:00 EST]]></pubDate>
<description><![CDATA[Geoff Irvine, SAFC Hitech, reviews the development and introduction of high- k layers into the semiconductor industry, and what the next 20 years might bring in the next-generation high- k and ultra-high- k layers and precursors.]]></description>
</item>
</channel>
</rss>
