Silicon Epitaxy
Silicon Epitaxy news and technical articles from Solid State Technology Magazine. Search Silicon Epitaxy latest and archived news and articles
-
Soitec claims lower-cost GaN template wafers for LED fab with HVPE, partners with Silian
… Electric scale GaN engineered wafers to 6" Soitec developed HVPE at its Phoenix Labs, using production-proven silicon epitaxy equipment features and adding its gallium source and delivery system, said Chantal Arena, vice president and general …
-
Tackling power/performance trade-offs with silicon channel engineering
… advances that have been made in silicon epitaxy in recent years, it is now possible ..... nonsemiconductor layer” during silicon epitaxy , the resultant layer, though ..... nonsemiconductor layer during silicon epitaxy . Click here to enlarge image …
-
Simple wet cleaning improvements can meet new silicon surface preparation criteria
… regime, lower thermal budgets for processes like silicon epitaxy require bake temperatures to be < 800°C, and for ..... Andre, and F. Tardif, HF Last Cleaning Before Silicon Epitaxy , unknown publication source, based on technical …
-
Nocilis Materials launches SiGe foundry
… roughness, composition, strain amount (in-plane and perpendicular to the plane). Nocilis Materials AB uses silicon epitaxy - and characterization equipment. Web: www.nocilismaterials.com .
-
Shining more light in epitaxial thin-film silicon solar cells
… S. Reber, et al., ConCVD and ProConCVD: development of high-througput CVD tools on the way to low-cost silicon epitaxy , 24th EUPVSEC (2009), Germany, p2560. Els Parton received her engineering degree and PhD in biological sciences …
-
Fine control of low-temperature CVD epitaxial growth
… Greenlief, S.R. Kasi, M. Offenberg, "Kinetics of Silicon Epitaxy using SiH 4 in a Rapid Thermal Chemical Vapor Deposition ..... Arkadii V. Samoilov is a program manager of the Silicon Epitaxy Technology Development Laboratory in the Epi Substrate …
-
A new generation of IC processing: Low-power, high-performance SOI CMOS
… is growing for SOI substrates as the successor to silicon epitaxy for current CMOS scaling and ultimately for high ..... thickness, the gate is patterned, and a selective silicon epitaxy is achieved to raise the source/drain regions …
-
Advanced R&D: CMOS: How far can it go?
… solubility limit of these atoms in silicon. Selective silicon epitaxy of the channel has also been suggested to achieve ..... punch-through would be an issue. In this case, silicon epitaxy can also be used to achieve low surface concentration …
-
Diverse CMP needs require a dielectric selectivity platform
… oxide hardmask deposition, gate lithography, and etch; 3) extension implant; 4) spacer formation; 5) selective silicon epitaxy raised source/drain; 6) source/drain implant and activation anneal; 7) source/drain silicidation with Co …
-
People
… named advanced materials delivery system product manager. He previously held management positions in plasma strip and silicon epitaxy at Mattson Technology. Hyman Click here to enlarge image Everett Charles Technologies, Pomona, CA, has named Keith …
