Nmos
Nmos news and technical articles from Solid State Technology Magazine. Search Nmos latest and archived news and articles
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Strained silicon and HKMG take the stage at 22nm
… metal films to tune work functions for nMOS and pMOS, are difficult to maintain because ..... few generations, but at the 22nm node, nMOS strain technology will likely be introduced ..... two approaches under consideration for nMOS strain: epitaxial Si:P and epitaxial …
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Scatterometry measurement for gate ADI and AEI CD of 28nm metal gates
… were two targets in one field: one for an NMOS structure and a second for a PMOS structure ..... MCD as function of focus and exposure for NMOS target (top) and PMOS target (bottom ..... versus focus and energy exposure for both NMOS and PMOS targets are displayed in Fig …
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imec advances CMOS beyond silicon to Ge, III-V
… Initially imec used germanium for pMOS devices and III-V for nMOS devices. This had led to a whole new series of technologies, advancing ..... displays via-middle TSV process for die stacking Intel clarifies 32nm NMOS stress mechanism at IEDM 2011
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IEDM 2011 Preview: Chipworks' must-see picks for IEDM
… as noted in my last blog, Intel sheds some light on their NMOS stress mechanism seen in their 32nm process ( 34.4 ) -- or ..... Tech also talk finFET doping ( 35.6 ), this time specific to NMOS . The last paper of the session ( 35.7 ) has NU Singapore and …
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Thermal wafer processing for Ni(Pt)Si contacts beyond 45nm
… this diffusion occurs underneath the gate. Mainly observed on NMOS , this NiSi encroachment (also called piping) is a strong function ..... optimized RTP1 processes all end up with low leakage on both NMOS and PMOS structures. On PMOS process the two RTP1 spike anneals …
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Self-powered electronics: Achievements and challenges @ IEDM
… SEMATECH’s SILC ~10% and HKMG lifetime; ALD BeO a viable gate stack IPL solution Cornell, SRC develop RF MEMS technologies IBM displays via-middle TSV process for die stacking Intel clarifies 32nm NMOS stress mechanism at IEDM 2011
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imec claims RRAM is smallest based on HfO2
… s SILC ~10% and HKMG lifetime; ALD BeO a viable gate stack IPL solution Cornell, SRC develop RF MEMS technologies IBM displays via-middle TSV process for die stacking Intel clarifies 32nm NMOS stress mechanism at IEDM 2011
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The era of fully-depleted devices
… metal gates, TiN and TaAlN, and the doping of two ground planes (GP) below the BOX in order to obtain the four Vts for both nMOS and pMOS without back bias as shown in Fig. 4 a. The use of ultra-thin SOI and buried oxide (UTBB) substrate for planar …
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IMEC discusses major projects at SEMICON West
… channel control is much better, and the structure is scalable, but developments are still ongoing, especially on the PMOS/ NMOS interaction. In memory activities, imec is working on resistive RAM (RRAM) endurance (number of cycles) and materials …
