Multichip Packaging
Multichip Packaging news and technical articles from Solid State Technology Magazine. Search Multichip Packaging latest and archived news and articles
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IMAPS 2009: Fusion bonding for 3D/TSV, wafer-level/multichip packaging for MEMS
Presentations at this year's International Symposium on Microelectronics (IMAPS, San Jose, Nov. 1-5) included discussion of TSV/3D integration challenges and temporary bonding steps qualified for different process flows, and a wafer-level packaging (WLP) encapsulation process and stacked multi-chip
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IMAPS 2009: Fusion bonding for 3D/TSV, wafer-level/multichip packaging for MEMS
Presentations at the International Symposium on Microelectronics (IMAPS, Nov. 1-5) included discussion of through-silicon via (TSV) /3D integration challenges and temporary bonding steps qualified for different process flows, and a wafer-level packaging (WLP) encapsulation process and stacked
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Multichip Packaging , Business and logistical issues
Continuing functional enhancement of portable consumer and computing products challenges electronics industry OEMs to provide these products in smaller and lighter form factors.
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Professor Rao Tummala to Present Keynote at 2009 International Wafer-Level Packaging Conference (IWLPC)
… technologies as the first plasma flat panel display based on gas discharge, the first and next three generations of multichip packaging based on 35-layer alumina and 61-layer LTCC with copper and copper-polymer thin film, and materials for …
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10th Anniversary Insights New (?) and emerging (?) technologies
… is an MCM. The history of multichip packaging is long and continuous. Known ..... a serious problem for any multichip packaging approach because defective ..... enabled significant strides in multichip packaging applications. 3-D Packaging …
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TSMC approves 300mm WLP packaging plan, 0.18-micron upgrade
… preparation for work on AMD's Fusion microprocessor which has integrated graphics capabilities, and for which multichip packaging and wafer-level packaging methods would reduce production costs and manufacturing risks. TSMC has been the major …
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Increased co-design needed to advance electronics miniaturization
… specifically cellular phones. While semiconductor packaging technologies such as chip-scale packaging (CSP) and multichip packaging (MCP) have driven the miniaturization of wireless products over the past several years, there is significant …
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TSMC increasing Vanguard stake to boost 200mm plans
… preparation for work on AMD's Fusion microprocessor which has integrated graphics capabilities, and for which multichip packaging and wafer-level packaging methods would reduce production costs and manufacturing risks.
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2D, 3D and Beyond: Inspecting Stacked Die in MCPs
… inspection capability, which can detect existing defects and preempt further process investment, is multiplied in multichip packaging (MCP) applications by the large investment already made in multiple, fully processed die and the unrecoverable …
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System-in-package update
… committee (JC-63) has been formed to address the need for cooperation in the SIP area by working on standards for multichip packaging . In general, this and other efforts promoting cooperation among the many types of participants in SIP are needed …
