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than 60•. This type of microstructure is shown in the SEM micrograph in Fig. 2a. The dark grains in this figure, which are ..... microstructure will have a de-wetted Y-Al-O phase as shown in the micrograph in Fig. 2b. • These same basic considerations for sintering
60°C. This type of microstructure is shown in the SEM micrograph in Figure 4A. The dark grains in this figure, which are ..... microstructure will have a de-wetted Y-Al-O phase as shown in the micrograph in Figure 4B. Figure 5. Microstructure sintered at 1675C
then grown on each elevated area, with minimal separation of neighboring crystals. Image: Perspective scanning electron micrograph (SEM) of an 8um-tall array showing germanium crystals grown on silicon pillars. SOURCE: ETH Zurich. The researchers
transistor on Fujitsu Semiconductor's low-power CMOS process is shown in Figure 1. The cross sectional transmission electron micrograph (TEM) shows the transistor fabricated on a planar bulk silicon structure. Figure 1. SuVolta's cross-section TEM The
instrumentation with a nanomechanical cantilever probe and nanophotonic interferometer on a chip. Figure. Scanning electron micrograph (SEM) of the cantilever-microdisksystem. A calculated z-component of the magnetic field is overlaid on the structure
and slowly peeling back the stamp. (v)–(vii) Sequential transfer printing of green and blue QDs. b, Fluorescence micrograph of the transfer-printed RGB QD stripes onto the glass substrate, excited by 365 nm UV radiation. The team began by modifying
by the two lines. The beads start out suspended in salt water above the valves before being trapped in the array. Figure. Micrograph of magnetic microfluidic chip developed by the NIST and CU. Brief pulses of electrical current in the two orange lines generate
a range of dielectric structures to optimize device design. Figures. In this schematic (top) and transmission electron micrograph (TEM image, bottom), a Si nanowire is shown surrounded by a stack of thin dielectric layers. NIST scientists determined
a range of dielectric structures to optimize device design. Figures. In this schematic (top) and transmission electron micrograph (TEM image, bottom), a Si nanowire is shown surrounded by a stack of thin dielectric layers. NIST scientists determined