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(June 5, 2007) SAN DIEGO Since carbon nanotubes (CNTs) tend to grow with erratic kinks and bends in the tube structure, a group of engineers from Stanford University has devised circuit-simulation algorithms that eliminate bad connections caused by errant CNTs. The work, which involves fine grids
to research next-generation flip-chip and substrates to address "IC-to-package-to-board" packaging interconnect issues for ICs at the 32nm node and beyond. The two groups are setting up an industrial affiliation program to explore
reflects interconnects' maturity Fourteen papers participated in the poster session, covering the whole spectrum of interconnect issues . I particularly enjoyed Matt Spuller's description of a PECVD boron nitride material from Applied Materials
generation flip chip and substrate technology. The program addresses key IC-to-package-to-board packaging interconnect issues , specifically how to accommodate for fine pitch for 32-nm ICs and beyond.
been established, one for design/test issues led by the University of California at Berkley and a second for interconnect issues led by the Georgia Institute of Technology. R&D agendas are focused on new technologies for commercialization
to-BGA Adapters Click here to enlarge image These BGA-to-BGA adapters are designed to address a variety of interconnect issues . They can be used to convert difficult-to-assemble fine-pitch BGAs to footprints that are more compatible
Devices and Materials, held in Tokyo. Jim Meindl, professor at the Georgia Institute of Technology, discussed interconnect issues that will affect future device generations. For late 1980s 1µm technology, the intrinsic switching delay of an
floor to take a closer look. Interconnect Systems Inc. had a slew of adapters with solutions to many kinds of interconnect issues , including die shrinks, re-designs, faulty designs, and other situations needing a fix that happen all the
package designers building a single stacked-die package that combines various system functions is die-to-die interconnect issues . Most package designers analyze the die-to-pin connection by reviewing the interconnect performance from the
capabilities, the use of cryogenic gases, and other alternative chemistries. As the industry works on resolving interconnect issues for deep sub-micron generations, Sorenson said he will also be exploring solutions to those "longer range needs