Die Stacking
Die Stacking news and technical articles from Solid State Technology Magazine. Search Die Stacking latest and archived news and articles
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World News
BUSINESS TRENDS VLSI tool champs prove customer service matters VLSI Research's out with its annual "Best supplier" rankings, and there's a tie atop the leaderboard. Nine-time champ Varian Semi. Equip. Assoc. and first-timer Novellus both scored 8.18 in the "large supplier" category of chipmaking
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TI achieves volume production with stacked clip-bonded QFN
Texas Instruments has shipped more than 30 million units of its PowerStack packaging technology, a combination of chip stacking and clip bonding that is designed to improve performance and chip densities in power management devices.
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SEMI convenes system-in-package summit alongside SEMICON Taiwan
SEMI will hold the first-ever SiP Global Summit, September 7-9, co-located with SEMICON Taiwan. Three forums cover system in package (SiP) test, the "3D IC era," and the requirements of mobile electronics.
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STATS ChipPAC widens fan-out WLP configurations with TSVs, IPDs
STATS ChipPAC says integrating through-silicon vias with passive devices and its eWLB technology addresses complex design issues, shrinking lithography nodes, and increased performance demands for mobile and consumer applications.
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GA Tech's Rao Tummala recognized with major IEEE packaging award
IEEE's Field Award for microelectronics packaging contributions goes to GA Tech's Rao Tummala, a longtime IBM research who pioneered packaging integration research and globalization of electronic packaging.
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Silicon interposers: building blocks for 3D-ICs
Silicon interposers seem set to stay as a valid alternative implementation to full 3D-IC designs. Matthew Hogan, Mentor Graphics, Wilsonville, OR
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Endicott Interconnect update: Defense electronics contracts
Endicott Interconnect Technologies released an update on its defense electronics development and production and sustainment contracts, which totalled $101 million.
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IMEC, Cadence automate 3D IC design test
Imec and Cadence say they have developed a design-for-test and automatic test pattern generation technology to more easily test 3D stacked ICs with through-silicon via (TSV) functionality, adding only "negligible" area costs.
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NEMS sensor improves AFM
The US National Institute of Standards and Technology's (NIST) Center for Nanoscale Science and Technology (CNST) has improved atomic force microscopy (AFM) by replacing the microscope's optical instrumentation with a nanomechanical cantilever probe and nanophotonic interferometer on a chip.
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Microsemi names Carsem supplier of the year
Carsem received Microsemi Corporation's Best Supplier of The Year Award, for assembly and test services that were provided by the Carsem factory located in Suzhou, China.
