3d Stacking
3d Stacking news and technical articles from Solid State Technology Magazine. Search 3d Stacking latest and archived news and articles
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Honeywell taps Tezzaron Semiconductor to stack rad-hard die
December 9, 2011 -- Honeywell Microelectronics will use Tezzaron's 3D stacking on Honeywell’s S150 process on radiation-hardened (rad-hard) aerospace electronics components. Honeywell will use Tezzaron …
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Package-on-package (PoP) track at SMTAI
… host sessions and courses with Amkor, Research in Motion, and TechLead Corporation on package-on-package (PoP) 3D stacking at SMTA International (SMTAI), October 16-20 in Fort Worth, TX. Lee Smith, Amkor Technology, will present …
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3M, IBM to make 3D chip adhesives
Forget " 3D stacking " -- the two companies say a special electronic "glue" applied to the wafer will help stack dozens of chips into a "silicon skyscraper" that will be much faster and more efficient than current chip technology.
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DRIE expands from MEMS to advanced packaging and more applications
… devices that will also use DRIE. In the years 2005+, the emerging of the Through Si Vias (“TSV”) technology for 3D stacking gave a breath to the DRIE technology. Today, DRIE is used through three different technology platforms: -- Interposers …
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Interposer supply/ecosystem examined at IMAPS Device Packaging
… and as such probably would not be a broadly accepted solution for low cost mobile products which would prefer straight 3D stacking . In response to the Qualcomm statement, TSMC’s Yu responded that indeed the addition of an interposer added cost to the …
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Applied Materials' Onyx treatment restores lost carbon, strengthens film structure
… The product targets the challenges associated with 3D packaging applications and technologies such as copper pillar, 3D stacking , and lead-free soldering. The solution decreases the dielectric constant value by up to 20%, thereby reducing …
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22nm requires foundry-to-packaging-house cooperation
… servers and network systems. Another option that may see greater adoption at the 22nm technology node is some form of 3D stacking of memory and logic with TSVs. 3D TSV is often touted as the way to achieve higher bandwidth, greater performance …
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2.5D announcements at the Global Interposer Tech conference
… is fabricating the package substrate. Ramalingam emphasized that the interposer solution was necessary (vs. full 3D stacking ) to insure proper thermal performance. Kumar Nagarajan of Xilinx called the use of the interposer the "low-risk …
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Will 22nm need a mid-node?
… increased device performance while reducing the total package form factor by utilizing through silicon vias (TSV) for 3D stacking . At 20nm, over 90% of leading-edge logic chips will require bump packaging solutions. Memory companies are aggressively …
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STATS ChipPAC widens fan-out WLP configurations with TSVs, IPDs
… have promoted an "all-silicon" packaging concept for several years, calling for integration of wafer-level and 3D stacking technologies to bring tighter node silicon, vertical die integration, and embedded passives together. Read about …
