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  1. CEA-Leti launches 3D semiconductor packaging platform

    Article

    Tue, 31 Jan 2012

    corresponding to the initial technical requirements of Leti customers. Figure 1. The Open-3D offer from CEA-Leti. 3D semiconductor packaging can offer performance, form factor, and cost benefits to bio/medical, aeronautics and space, consumer applications

  2. Optomec expands aerosol jet lab for 3D semiconductor packaging, PV, other device formation

    Article

    Thu, 19 Jan 2012

    enhance performance of current electronic devices, as well as to enable the creation of next generation products, such as 3D semiconductor packaging , high efficiency solar cells and solid oxide fuel cells . Also read: Optomec aerosol jet printing featured

  1. AMAT, Singapore's microelectronics institute open 3D semiconductor packaging R&D lab

    Article

    Wed, 7 Mar 2012

    Applied Materials Inc. (AMAT) opened the new Centre of Excellence in Advanced Packaging at Singapore’s Science Park II with its partner in the endeavor, A*STAR.

  2. Georgia Tech targets thin 3D packaging with new consortium

    Article

    Wed, 11 Apr 2012

    Georgia Institute of Technology (Georgia Tech) Packaging Research Center (GT-PRC) proposes a new consortium on 3D semiconductor packaging called 3D ThinPack (THInPack) for ultra-miniaturized 3D heterogeneous, RF, digital and power modules in

  3. Silicon Genesis wafering tool designed for solar, LED, packaging sectors

    Article

    Mon, 19 Mar 2012

    system for fabricating thin-silicon solar wafers, as well as high-brightness light-emitting diode (HB-LED) , and 3D semiconductor packaging wafers. The system tailored for silicon, GaAs, germanium, SiC, GaN and sapphire materials. The new GenII

  4. Shin-Etsu Chemical joins EVG wafer bonding supply chain

    Article

    Wed, 14 Mar 2012

    Shin-Etsu Chemical Co. Ltd. into its open platform for temporary bonding/debonding (TB/DB) materials supporting 3D semiconductor packaging . Shin-Etsu will work with customers to commercialize 3D IC packaging via wafer bond/debond in volume manufacturing

  5. ULVAC CVD-Co, -Ni system suits 3D gate, MEMS fab

    Article

    Thu, 1 Dec 2011

    ULVAC Inc. developed the ENTRONTM-EX2 W300 CVD-Ni/CVD-Co system for CVD-Ni and CVD-Co silicidation of 3D semiconductor gates and MEMS . The system is a response to a semiconductor industry transition from PVD to CVD in advanced 3D gate structure

  6. TSV zen comes down to wafer processing balance

    Article

    Tue, 26 Jul 2011

    July 26, 2011 -- 3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry

  7. SEMATECH creates 3D packaging standards development forum

    Article

    Mon, 7 Nov 2011

    November 7, 2011 -- SEMATECH has created an online 3D Standards Dashboard, allowing 3D semiconductor and MEMS interconnect professionals to exchange standards activity information. This Dashboard, managed by SEMATECH's 3D Enablement

  8. SEMATECH survey on 2.5D, 3D IC; gaps in the via-mid ecosystem

    Article

    Thu, 14 Jul 2011

    July 13 at 1:50PM]). Arkalgud discusses the high-volume manufacturability issues and gaps in both 2.5D and 3D semiconductor technologies with respect to backside processing and wafer bonding, thinning, and handling. The figure is a summary

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