3d Chip
3d Chip news and technical articles from Solid State Technology Magazine. Search 3d Chip latest and archived news and articles
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3M, IBM to make 3D chip adhesives
Forget "3D stacking" -- the two companies say a special electronic "glue" applied to the wafer will help stack dozens of chips into a "silicon skyscraper" that will be much faster and more efficient than current chip technology.
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Leti on 3D CMOS and photonics interconnect
November 28, 2011 -- Leti’s recent work includes nanophotonics communications devices, which use 3D chip interconnect. ElectroIQ.com caught up with Hughes Metras, director, North America, for Leti, at the IEEE San Francisco Bay …
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AMAT, Singapore's microelectronics institute open 3D semiconductor packaging R&D lab
… technology to be used by IME’s leading researchers in 3D chip packaging. While it supports research collaboration between ..... Excellence in Advanced Packaging. The research will cover 3D chip stacking, such as through silicon via (TSV) formation …
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AMAT BSI image sensor CVD tool operates at low processing temps
… Producer Optiva CVD system can also be used to deposit conformal insulating liners for through-silicon vias (TSVs) in 3D chip packaging. In this application, low process temperatures protect the adhesive used to bond the wafer to its temporary …
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3M debuts high-capacitance ECM for IC packaging, RF, other apps
… inch 2 capacitance density range. The ECM material is halogen-free and RoHS compliant. Also read: 3M, IBM to make 3D chip adhesives The material matches the needs of increased fidelity and rapid miniaturization in electronic devices, said Abhay …
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IBM fabs Micron memory cube with TSV tech
… are rolling out will have applications beyond memory, enabling other industry segments as well. In the next few years, 3D chip technology will make its way into consumer products, and we can expect to see drastic improvements in battery life and …
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SEMICON West 2011: New product roundup
… costly photolithography steps and related processing, marking a fundamental advance in the construction of interposers for 3D chip packages. The technology accommodates thicker wafers, eliminating the need for wafer carriers and allows for highly scalloped …
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Imec ITF: The next wave of applications, with chips designed in 3D
… imec May 25, 2011 - At the Imec Technology Forum (ITF, May 25-26 in Brussels), Pol Marchal introduced his talk on 3D chip technology by recalling some of the powerful trends in the semiconductor market. Each trend points to the next wave of …
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ASICs and FPGAs could take a lesson from autos, says Xilinx
… NRE. Crossover SoCs should bridge the gap between ASICs and FPGAs. Bolsens finishes the interview with a focus on 28nm 3D chip architecture -- particularly the confusion around supply chain handoffs. "There has to be a lot more agreement on roadmaps …
