This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent® Diagnosis and Tessent YieldInsight® software products. ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed, mature yield is suboptimal, and product quality may suffer, thereby threatening a manufacturer’s profitability. Diagnosis-driven yield analysis is a methodology that leverages production test results, volume scan diagnosis, and statistical analysis to identify the cause of yield loss prior to failure analysis. This methodology can reduce the root cause cycle time with 75-90%. The methodology can be expanded with DFM-aware yield analysis to help separate design and process related yield limiters.

This White Paper brought to you by Mentor Graphics.

The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embedded IP, the new IEEE P1687 standard 1 is being defined by a broad coalition of IP vendors, IP users, major ATE companies, and all three major EDA vendors. This new standard, also called IJTAG, is expected to be rapidly and widely adopted by the semiconductor industry. The P1687 standard will enable the industry to develop test patterns for IPs on the IP level without having to know how the IP will be embedded within different designs. Mentor Graphics and NXP Semiconductors (NXP) worked together to implement P1687 on mixed-signal IPs in a 65 nm automotive design. The results demonstrate the significant advantages of P1687 over the current IEEE 1149.1 (JTAG) 2 test methodology, both in automating the test pattern development and in reducing test setup data volume by more than 50%.

This White Paper brought to you by Mentor Graphics.

Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are interested in statistical analysis of volumes of high-quality diagnosis results to determine yield limiters. To be of value for both engineers, a diagnosis tool needs to be

• Accurate,
• With high resolution and
• Meaningful defect classifications.

This Technology Paper brought to you by Mentor Graphics.