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September 20, 2011 -- D2S announced a mask-wafer double simulation accelerated workstation for R&D exploration, bit-cell design, hot-spot analysis and mask defect categorization at the SPIE Photomask Technology conference (i.e., BACUS, 9/19-9/22/11, Monterey, CA). Called TrueMask DS, the new tool targets mask shops and wafer fabs that are qualifying and optimizing 20nm node and below semiconductor designs. At these nodes, the assist features on the photomasks are smaller than 80nm and can no longer be faithfully produced. The purpose of the new simulation tool is to enable the efficient exploration of the various trade-offs including complex optical proximity correction (OPC), inverse lithography technology (ILT), source mask optimization (SMO), and the cost and turnaround time of masks for critical circuits.
In the podcast interview below, Aki Fujimura, CEO, D2S (and managing company sponsor of the eBeam Initiative), describes the product’s effect on mask writing, costs and wafer yield at 20nm and below.
