WAFER LEVEL PACKAGING

Flip chip, bare die and other wafer-level package architectures.

WAFER LEVEL PACKAGING ARTICLES

Partnership forms to commercialize advanced photonic chip innovations

Nov 29, 2011 The Institute of Microelectronics, a research institute of Singapore's A*STAR, plans to commercialize key innovations in silicon photonic chips designed to support high-speed, h...

OSRAM envelops LED chip in reflective package

Nov 29, 2011

OSRAM Opto Semiconductors introduced the Oslon Square LED for lighting applications, packaged enclosed in a reflective layer to boost light output.

DAC seeks speakers bureau experts

Nov 23, 2011 The Design Automation Conference (DAC) is soliciting semiconductor industry experts for participation in invited sessions, panels, and other events at the 49th DAC, June 3-7, 20...

STATS ChipPAC expands wafer-level chipscale packaging in Taiwan

Nov 17, 2011

STATS ChipPAC Ltd. completed the expansion of its 300mm wafer bump and wafer-level chipscale packaging (WLCSP) operation in Taiwan.

Report examines fan-out wafer-level packaging momentum, assembly pricing trends

Nov 16, 2011 Fan-out wafer-level packaging (FO-WLP) is gaining momentum as an option for devices with large numbers of I/Os, vs. going finer-pitch to keep using conventional fan-in technolog...

SUSS MicroTec sends equipment to SVTC in MEMS, 3D IC dev partnership

Nov 15, 2011

Nanotechnology accelerator SVTC Technologies partnered with SUSS MicroTec on wafer-level packaging for MEMS, and 3D IC bonding technology development.

PACKAGING INDUSTRY NEWS

Keithley Instruments upgrades semiconductor test software suite

Jan 26, 2012 Keithley Instruments Inc. upgraded the capabilities of its Automated Characterization Suite Test Environment to ACS Version 4.4. The software is used with se...

BSE Group achieves milestones in semiconductor equipment financing biz

Jan 26, 2012 Test Advantage Capital Group, a business of BSE Group, surpassed $150M in its portfolio of semiconductor manufacturing equipment under management. Boston Sem...

Metallization processes for standardized wide-IO memory applications

Jan 26, 2012 A new generation of nanotechnology-based wet-process films provides process simplification, performance boost and cost reduction beyond TSVs. Claudio Truzzi,...

3D MID sensor fabricated with Ticona laser-activated LCP circuits

Jan 25, 2012 2E mechatronic GmbH & Co. KG designed a 3D molded interconnect device flow sensor that uses Ticona's Vectra E840i LDS laser-activated LCP for electronic ...

Presto Engineering semiconductor service hub opens in Israel

Jan 24, 2012 Presto Engineering, integrated semiconductor test and product engineering services provider, opened its newest Hub to serve the semiconductor design communit...

FINANCIALS

PACKAGING VIDEOS

EIQ2 SST

PACKAGING WHITE PAPERS

Preventing the Destructive Potential of Partial Discharge on HV Optic Devices

The Partial Discharge phenomenon has been plaguing the electrical and electronic industries for many years, by damaging equipment and increasing production c...
Sponsored by

Enabling Thinner Packages through Novel Materials Innovations

According to a new industry report, thinned wafers will comprise the majority of wafers in the device market by 2016. (1) The study indicates that memory and...
Sponsored by

New Pressureless, High UPH Silver Sintering Technology Charges Up Power Device Manufacturers

Silver sintering is not a new technology. In fact, it has been around for some time. What is new, however, is a groundbreaking material innovation that now a...
Sponsored by

PACKAGING WEBCASTS

FREE WEBCAST: Lens Tilt in Small Auto-Focus Cameras

This webinar will provide an introduction to miniature auto-focus camera technology and voice coil motors.

FREE WEBCAST: Light and Color Measurement of Today's LED Technology

The seminar is an ideal fit for anyone interested in characterizing and communicating the light and color properties of LED’s accurately.

MOST READ

© 2011. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS